Analog Devices Inc. ADV3002BSTZ-RL
- Part No.:
- ADV3002BSTZ-RL
- Manufacturer:
- Analog Devices Inc.
- Category:
- Video Processing
- Package:
- 80-LQFP
- Datasheet:
-
ADV3002BSTZ-RL.pdf
- Description:
- IC VIDEO SWITCH 80LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,685
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
ADV3002BSTZ-RL from Analog Devices is a 4:1 HDMI/DVI switch IC with integrated TMDS equalization, DDC/CEC buffering, and EDID replication - designed for high-fidelity video routing in consumer A/V systems. It supports data rates up to 2.25 Gbps, pixel clocks up to 225 MHz, and provides ±8 kV ESD protection on HDMI inputs. Its role is to consolidate four HDMI sources into one sink while maintaining signal integrity over long cables (e.g., >20 m of 24 AWG at 2.25 Gbps).
For engineers reviewing the ADV3002BSTZ-RL datasheet, ADV3002BSTZ-RL pinout, ADV3002BSTZ-RL application, or ADV3002BSTZ-RL equivalent, key selection criteria include TMDS equalization capability, EDID replication architecture, hot-plug detect pulse control, and compatibility with HDMI 1.4a and DVI 1.0 standards in space-constrained LQFP layouts.
Technical Context
The ADV3002BSTZ-RL implements a fully buffered 4-input/1-output TMDS switching core with programmable on-chip 50 Ω input terminations and selectable 4 dB or 16 dB high-frequency equalization. Its loss-of-signal (LOS) detection operates down to 5 MHz and triggers on clock amplitude thresholds as low as 35 mV at 225 MHz.
It integrates bidirectional DDC buffers compliant with I²C timing, CEC line buffering with 26 kΩ integrated pull-ups, and a 5 V combiner that powers EDID/CEC circuitry even when local system power is off. Channel selection is controlled via parallel SEL[1:0] or I²C interface, with reset and output enable (TX_EN) pins supporting system-level power management.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Max Data Rate | 2.25 Gbps per channel - enables full 1080p60 RGB 8-bit video with HDCP over HDMI/DVI links. |
| Pixel Clock Support | 25 MHz to 225 MHz - covers VGA through 1080p60 and UXGA resolutions. |
| Input Equalization | 16 dB boost at 1.5 GHz - compensates >20 m of 24 AWG cable at 2.25 Gbps without external EQ circuitry. |
| ESD Protection | ±8 kV HBM on TMDS inputs - meets IEC 61000-4-2 Level 4 for robust front-panel HDMI port handling. |
| EDID Replication | Single external EEPROM shared across all 4 ports - eliminates 3 redundant EDID EEPROMs and associated PCB area. |
| Hot Plug Detect | Programmable pulse width or manual HPD control - ensures reliable sink-side plug detection during source switching. |
| Supply Voltages | AVCC = 3.3 V ±10%, AMUXVCC = 5.0 V, AVEE = 0 V - dual-rail operation isolates analog and auxiliary domains. |
| Operating Temp | 0°C to +85°C - qualified for commercial A/V equipment including set-top boxes and projectors. |
Pinout & Package
ADV3002BSTZ-RL is housed in an 80-lead, 14 mm × 14 mm RoHS-compliant LQFP package with exposed thermal pad. Pin functions are validated per Analog Devices Rev. B datasheet Figure 2 and Table 6.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN_A_CLK+/− to IN_D_DATA2+/− | TMDS Input Differential Pairs | Four independent HDMI/DVI input lanes (A–D), each with clock + 3 data channels; support differential swing 150–1200 mV. |
| OUT_CLK+/−, OUT_DATA0–2+/− | TMDS Output Differential Pairs | Single switched output lane; internal 50 Ω back-termination enabled by default for HDMI-compliant routing. |
| SEL[1:0], TX_EN, RESETB | Parallel Control Inputs | Select active input (00–11), enable/disable TMDS output, and reset configuration registers - no external logic required. |
| DDC_SDA_COM/DDL_SCL_COM | Common DDC Bus Interface | Bidirectional I²C bus buffer (5 V tolerant) - connects host MCU or sink to all four source DDC lines simultaneously. |
| CEC_IN/CEC_OUT | CEC Line Interface | Bidirectional CEC channel with integrated 26 kΩ pull-up - enables system-wide remote control passthrough without external resistors. |
| EDID_SDA/EDID_SCL | EDID EEPROM Interface | Direct connection to single external EDID EEPROM - SRAM-based replication allows concurrent read access from all 4 ports. |
| P5V_A–P5V_D | HDMI Source 5 V Supplies | Isolated 5 V inputs per source - powers HPD circuits and enables hot-plug detection even when main system is off. |
| HPD_A–HPD_D | Hot Plug Detect Outputs | Open-drain outputs per source - generate standardized HPD pulses upon channel switch or manual trigger. |
Key Features
| Feature | Design Value |
|---|---|
| Input Equalizer with 16 dB Boost | Compensates signal loss in >20 m HDMI cables at 2.25 Gbps - eliminates need for external redrivers in mid-range A/V gear. |
| EDID Replication Engine | On-chip SRAM stores one EDID block and serves it to all four HDMI inputs - reduces BOM count and simplifies firmware updates. |
| 5 V Combiner Circuit | Supplies EDID replicator and CEC buffer from any active P5V_x rail - maintains CEC/EDID functionality during system standby. |
| Programmable Hot Plug Pulse | Configurable pulse width or direct manual HPD assertion - ensures sink-side detection reliability across diverse display firmware. |
| Integrated CEC Pull-Up Resistors | 26 kΩ on-chip pull-ups - removes requirement for external resistors and improves layout density in compact HDMI switch designs. |
| Loss-of-Signal Detection | Monitors TMDS clock amplitude down to 35 mV at 225 MHz - enables fast failover or UI alerts when source signal degrades. |
Applications
| HDTV Set Input Switching | Projector Multi-Source Hub |
|---|---|
|
Use Scenario: Consumer HDTV with four HDMI inputs (cable box, Blu-ray, game console, streaming stick) routes selected source to internal display processor. IC Role / Device Role / Timing Role: ADV3002BSTZ-RL acts as the primary TMDS multiplexer and EDID manager - handles hot-plug events, equalizes long internal traces, and presents unified EDID to all sources. Use Value: Eliminates need for four discrete EDID EEPROMs and external CEC pull-ups; reduces PCB layer count via integrated termination and buffering. |
Use Scenario: Commercial projector with HDMI, DisplayPort (via adapter), PC, and media player inputs requires seamless switching without display re-negotiation delays. IC Role / Device Role / Timing Role: ADV3002BSTZ-RL serves as the HDMI front-end switch - performs real-time TMDS equalization, DDC arbitration, and synchronized HPD signaling across sources. Use Value: Enables sub-500 ms source switching with retained EDID handshake and zero-frame-drop video handoff via deterministic LOS detection. |
| A/V Receiver Video Matrix | Set-Top Box HDMI Passthrough |
|
Use Scenario: High-end AV receiver aggregates HDMI sources before sending to TV or projector, requiring simultaneous DDC access and CEC passthrough. IC Role / Device Role / Timing Role: ADV3002BSTZ-RL functions as the DDC/CEC hub and TMDS switch - buffers all auxiliary channels, replicates EDID, and manages CEC command routing. Use Value: Supports full CEC device control tree (e.g., TV → AVR → Blu-ray) using single buffered CEC line; avoids auxiliary channel contention. |
Use Scenario: Cable/satellite STB with HDMI input (for recording) and HDMI output (for viewing) must pass through HDCP-encrypted content without breaking authentication. IC Role / Device Role / Timing Role: ADV3002BSTZ-RL operates as a transparent HDMI repeater - forwards TMDS, DDC, and CEC with cycle-accurate timing and embedded EDID caching. Use Value: Maintains HDCP 1.4 compliance via unmodified DDC traffic; enables "always-on" EDID availability even during STB boot or firmware update. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar HDMI/DVI switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TI TPD12S016RGER | Single-channel HDMI level shifter + ESD protection only - no switching, no EDID, no equalization. | Used for HDMI port protection only; cannot replace ADV3002BSTZ-RL's 4:1 mux or EDID replication. | Select only for ESD-hardened HDMI I/O buffering where switching and EDID functions are handled elsewhere. |
| Pericom PI3HDX412BDZDEX | 4:1 HDMI switch with 1.65 Gbps max rate, no integrated EDID replication or 5 V combiner. | Lacks EDID SRAM and CEC buffering - requires external EEPROM, pull-ups, and standby power management. | Consider for cost-sensitive designs below 1080p30 where EDID/CEC integration is not required. |
Compared with TI TPD12S016RGER and PI3HDX412BDZDEX, the ADV3002BSTZ-RL uniquely integrates equalization, EDID replication, CEC buffering, and 5 V combiner in one LQFP - reducing total component count by ≥7 devices and enabling true single-chip HDMI multiplexing for 1080p60 systems.
Availability
ADV3002BSTZ-RL is available at Aetrix Electronics and suitable for advanced television sets, projectors, A/V receivers, and set-top boxes requiring stable component supply, long-cable HDMI signal integrity, and EDID consolidation.
Supply support for ADV3002BSTZ-RL includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Analog Devices is a global leader in high-performance analog, mixed-signal, and digital signal processing semiconductors, serving precision instrumentation, communications, and industrial markets since 1965.
The ADV3002BSTZ-RL belongs to Analog Devices' high-speed interface product line, engineered specifically for HDMI/DVI signal routing in consumer A/V equipment where signal fidelity, integration density, and standards compliance are critical.
FAQ
What HDMI and DVI standards does the ADV3002BSTZ-RL support?
The ADV3002BSTZ-RL is HDMI 1.4a receive and transmit compliant and DVI 1.0 compliant. It supports HDCP 1.4 encryption handshaking via its buffered DDC channels and meets timing requirements for TMDS data rates up to 2.25 Gbps and pixel clocks up to 225 MHz - covering all resolutions from VGA to 1080p60 RGB 8-bit. The ADV3002BSTZ-RL does not support HDMI 2.0 or higher features such as 4K or HDR metadata transport.
How does the EDID replication function work in the ADV3002BSTZ-RL?
The ADV3002BSTZ-RL includes an on-chip SRAM that stores EDID data loaded from a single external EEPROM (via EDID_SCL/EDID_SDA pins) or from a system microcontroller. Once loaded, this EDID block is simultaneously accessible to all four HDMI input ports - eliminating the need for separate EEPROMs per port. The ADV3002BSTZ-RL asserts EDID_ENABLE to activate replication, and the common DDC bus (DDC_SDA_COM/DDC_SCL_COM) allows the sink to read EDID regardless of the selected source.
Can the ADV3002BSTZ-RL operate without external termination resistors on the TMDS outputs?
No - the ADV3002BSTZ-RL requires output termination. Internal 50 Ω terminations are enabled by default after reset, but if external terminations are also present (e.g., at the sink), the output current level must be reduced to 20 mA via the TX_OCL register bit. If only external terminations are used, internal termination must be disabled and output current set to 10 mA. Leaving outputs unterminated risks signal reflection, eye closure, and HDMI link failure - the ADV3002BSTZ-RL will not drive properly without proper termination.
What is the purpose of the 5 V combiner in the ADV3002BSTZ-RL?
The 5 V combiner in the ADV3002BSTZ-RL monitors all four P5V_A–P5V_D inputs and supplies regulated 5 V (AMUXVCC) to the EDID replicator and CEC buffer - even when the main system power is off. This ensures that EDID remains readable and CEC commands can be received and forwarded during standby mode, enabling true "always-on" HDMI features like CEC wake-up and sink-initiated EDID reads. The ADV3002BSTZ-RL uses this to maintain interoperability with TVs and displays that expect continuous EDID/CEC availability.
Does the ADV3002BSTZ-RL support automatic input termination control?
Yes - the ADV3002BSTZ-RL supports both manual and automatic input termination control. When configured for automatic mode, the device detects cable presence and signal integrity on each input and enables/disables the on-chip 50 Ω terminations accordingly. This is managed internally and requires no software intervention. In manual mode, termination state is set via the TMDS input termination control register. Both modes ensure optimal impedance matching for varying cable lengths and source output characteristics - a key feature distinguishing the ADV3002BSTZ-RL from basic passive switches.
ADV3002BSTZ-RL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Analog Devices Inc.
- Series:
- -
- Package/Case:
- 80-LQFP
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Switch
- Applications:
- Consumer Video
- Standards:
- HDMI 1.4a
- Control Interface:
- I2C, Serial
- Voltage - Supply:
- 3.0V ~ 3.6V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 80-LQFP (14x14)
ADV3002BSTZ-RL FAQ
1.How can I place an order for ADV3002BSTZ-RL through Aetrix?
Please submit a Request for Quotation (RFQ) for ADV3002BSTZ-RL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ADV3002BSTZ-RL reliable?
The price and inventory of ADV3002BSTZ-RL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ADV3002BSTZ-RL is usually 5 days.
3.What payment methods are accepted for ADV3002BSTZ-RL?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ADV3002BSTZ-RL transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ADV3002BSTZ-RL?
ADV3002BSTZ-RL orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ADV3002BSTZ-RL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ADV3002BSTZ-RL?
For technical support, including ADV3002BSTZ-RL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ADV3002BSTZ-RL requirements.
6.How does Aetrix verify that ADV3002BSTZ-RL is sourced from the original manufacturer or authorized distributors?
All ADV3002BSTZ-RL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ADV3002BSTZ-RL meets industry standards.
7.What is the process for return or replacement of ADV3002BSTZ-RL?
All ADV3002BSTZ-RL units undergo pre-shipment inspection (PSI). If there is an issue with ADV3002BSTZ-RL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ADV3002BSTZ-RL part is unused and in its original packaging.
Return procedure for ADV3002BSTZ-RL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
ADV3002BSTZ-RL Tags

-
HDMI2C1-6C1
STMicroelectronics

-
ADA4430-1YKSZ-R7
Analog Devices Inc.

-
LM1881MX/NOPB
Texas Instruments

-
SN75DP130SSRGZR
Texas Instruments

-
EQCO30T5.2
Microchip Technology
-
LMH1980MM/NOPB
Texas Instruments

-
EQCO30R5.D
Microchip Technology

-
SII9022ACNU
Lattice Semiconductor Corporation

-
SN65DP159RGZR
Texas Instruments

-
SN65DP159RSBR
Texas Instruments

-
SN65DP141RLJR
Texas Instruments

-
LMH0303SQ/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

