Broadcom Limited AFBR-5903Z
- Part No.:
- AFBR-5903Z
- Manufacturer:
- Broadcom Limited
- Category:
- Fiber Optic Transceiver Modules
- Package:
- Datasheet:
-
AFBR-5903Z.pdf
- Description:
- TXRX OPT FE MTRJ 2X5DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,364
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Product details
Overview
AFBR-5903Z from Avago Technologies is a 1300 nm FDDI/ATM/Fast Ethernet transceiver in a 2×5 MT-RJ package, operating at 125 MBd with PECL-compatible differential data I/O, -34.5 dBm receiver sensitivity at eye center, and full compliance with FDDI PMD (ISO/IEC 9314-3), ATM UNI 3.0, and IEEE 802.3u 100BASE-FX standards for multimode fiber backbone links.
For engineers reviewing the AFBR-5903Z datasheet, pinout, applications, or equivalent options, this page delivers verified electrical, optical, and mechanical specifications-including signal detect squelch behavior, +3.3 V single-supply operation, RoHS compliance, and MT-RJ receptacle integration-essential for FDDI, Fast Ethernet, and ATM 100 Mb/s system design and qualification.
Technical Context
The AFBR-5903Z integrates a 1300 nm InGaAsP LED transmitter and an InGaAs PIN photodiode receiver with transimpedance preamplifier and quantizer ICs, delivering differential PECL outputs (RD+/RD−, TD+/TD−) referenced to +3.3 V. Its signal detect (SD) output deasserts at −45 dBm input power and asserts at −33 dBm, enabling loss-of-signal monitoring with 1.5–2.4 dB hysteresis.
It supports 10–125 MBd signaling rates per FDDI/ATM requirements, exhibits ≤1.0 ns p-p data-dependent jitter (DDJ) and ≤2.14 ns p-p random jitter (RJ) at the receiver, and meets FDDI PMD Annex E system jitter allocations. The device uses a low-profile 2×5 DIP package with isolated solder posts for mechanical mounting and chassis grounding.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Operating Temp | 0°C to +70°C ambient; case temperature measurement point defined in Figure 2 |
| Supply Voltage | +3.135 V to +3.465 V; single rail powers both TX and RX sections |
| Receiver Sensitivity | −34.5 dBm avg at eye center (BER = 10⁻⁶); enables 2 km multimode fiber links |
| Transmitter Output | −15.7 dBm avg (BOL, 62.5/125 µm fiber); compliant with FDDI PMD optical budget |
| Signal Detect Threshold | Asserts at −33 dBm, deasserts at −45 dBm; provides 12 dB dynamic range for LOS detection |
| Data Interface | Differential PECL (ECL-shifted to +3.3 V); RD+/RD− and TD+/TD− require external 50 Ω termination |
| Jitter Performance | Receiver contributes ≤1.0 ns DDJ and ≤2.14 ns RJ p-p; meets FDDI PMD Annex E allocation |
Pinout & Package
The AFBR-5903Z uses a 2×5 DIP-style package with MT-RJ fiber receptacle, 10 signal pins, and two isolated solder posts for mechanical attachment and chassis grounding. Overall dimensions: 37.56 mm × 9.8 mm × 13.97 mm (L×W×H), with 0.550″ pin spacing and 750 µm fiber alignment pin spacing.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| Pin 1 | VEE RX | Receiver signal ground; must connect directly to low-inductance receiver ground plane |
| Pin 2 | VCC RX | +3.3 V receiver supply; requires local 10 µF + 10 nF decoupling per Figure 7 |
| Pin 3 | SD | Single-ended Signal Detect output; PECL logic "1" = valid signal (>−33 dBm), "0" = LOS (≤−45 dBm) |
| Pin 4 | RD− | Differential receiver data complement; requires external 50 Ω termination to VCC |
| Pin 5 | RD+ | Differential receiver data true; requires external 50 Ω termination to VCC |
| Pin 6 | VCC TX | +3.3 V transmitter supply; separate filtering recommended from VCC RX |
| Pin 7 | VEE TX | Transmitter signal ground; isolated from VEE RX in layout to minimize crosstalk |
| Pin 8 | TDIS | No connection (N/C); not functional on LED-based AFBR-5903Z (laser-only feature) |
| Pin 9 | TD+ | Differential transmitter data true; PECL input, requires 50 Ω source termination |
| Pin 10 | TD− | Differential transmitter data complement; PECL input, requires 50 Ω source termination |
Key Features
| Feature | Design Value |
|---|---|
| MT-RJ Integration | Industry-standard 2×5 DIP package with molded nonconductive MT-RJ port; eliminates need for MIC/R connector |
| Squelch Function | Receiver outputs (RD+/RD−) are actively forced to steady PECL high/low states when SD deasserts (input <−45 dBm) |
| FDDI/ATM/Fast Ethernet Compliance | Meets optical and electrical requirements of ISO/IEC 9314-3, ATM UNI 3.0 Section 2.3, and IEEE 802.3u 100BASE-FX |
| EMI Immunity | Internal shield over RX subassembly + conductive housing at signal ground; withstands 10 V/m RF field (10–450 MHz) |
| Process Compatibility | Wave solder and aqueous wash compatible; shipped with protective MT-RJ process plugs |
Applications
| FDDI Backbone Links | Fast Ethernet 100BASE-FX |
|---|---|
Use Scenario: 2 km multimode fiber interconnection between wiring closets and core switches in enterprise campus networks. IC Role / Device Role / Timing Role: Full-duplex optical transceiver implementing FDDI Physical Medium Dependent (PMD) layer with deterministic jitter control and signal detect monitoring. Use Value: Enables interoperable, standards-compliant FDDI links without requiring MIC/R connectors or larger 1×9 packages. | Use Scenario: Fiber uplink from desktop switch to aggregation switch in industrial automation control cabinets. IC Role / Device Role / Timing Role: 100BASE-FX PHY transceiver providing IEEE 802.3u-compliant optical interface with PECL-level signaling and integrated squelch. Use Value: Delivers −34.5 dBm receiver sensitivity and 125 MBd operation to support 2 km link reach over 62.5/125 µm fiber. |
| ATM 100 Mb/s UNI | Legacy Telecom Backhaul |
Use Scenario: Asynchronous Transfer Mode user-network interface in carrier-class DSLAM or broadband access multiplexer. IC Role / Device Role / Timing Role: ATM physical layer transceiver compliant with ATM Forum UNI 3.0 Section 2.3, using FDDI PMD as baseline. Use Value: Provides guaranteed BER performance and signal detect timing (ASMax ≤ 100 µs, ANSMax ≤ 350 µs) for ATM cell synchronization. | Use Scenario: Replacement transceiver in aging telecom central office equipment supporting legacy FDDI ring topologies. IC Role / Device Role / Timing Role: Drop-in optical interface for FDDI SM-PMD or LCF-PMD systems requiring 1300 nm LED-based transmission. Use Value: Maintains compatibility with existing FDDI MAC controllers while offering improved aging (<1 dB vs. industry 1.5 dB) and RoHS compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FDDI/ATM transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| HFBR-5903Z | Same 2×5 MT-RJ package, identical optical specs (−34.5 dBm sensitivity, −15.7 dBm Tx), but rated for 0°C to +70°C only; no extended shield option | Functionally identical for FDDI/100BASE-FX use; lacks AFBR-5903EZ's extended EMI shielding | Select HFBR-5903Z if EMI environment is controlled and cost optimization is prioritized over shielded variant |
| AFBR-5903AZ | Same architecture and pinout, but rated for −40°C to +85°C; otherwise matches AFBR-5903Z in all electrical/optical specs and package | Required for industrial or outdoor enclosures where ambient exceeds +70°C | Choose AFBR-5903AZ when operating temperature range must extend beyond commercial grade |
Compared with HFBR-5903Z and AFBR-5903AZ, the AFBR-5903Z offers identical core transceiver functionality and optical performance but is distinguished by its unshielded mechanical construction and strict 0°C to +70°C rating-making it optimal for cost-sensitive, thermally stable FDDI and Fast Ethernet deployments where extended temperature or enhanced EMI shielding is unnecessary.
Availability
AFBR-5903Z is available at Aetrix Electronics and suitable for FDDI backbone infrastructure, Fast Ethernet 100BASE-FX uplinks, ATM 100 Mb/s UNI interfaces, and legacy telecom backhaul systems requiring stable component supply and long-term obsolescence management.
Supply support for AFBR-5903Z includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Avago Technologies (now part of Broadcom) is a global leader in semiconductor optoelectronics, specializing in high-speed optical interconnects, RF, and analog solutions for datacom, telecom, and industrial markets.
The AFBR-5903Z belongs to Avago's FDDI/ATM transceiver product line, designed specifically to enable compact, standards-compliant, multimode fiber links for enterprise networking and legacy infrastructure modernization.
FAQ
What is the operating temperature range for the AFBR-5903Z?
The AFBR-5903Z is specified for ambient operating temperatures from 0°C to +70°C. This range corresponds to a transceiver case temperature of 0°C minimum to +85°C maximum under required airflow conditions, with the recommended case temperature measurement point shown in Figure 2 of the datasheet. It is not rated for extended industrial temperatures; for −40°C to +85°C operation, the AFBR-5903AZ variant must be used instead of the AFBR-5903Z.
Does the AFBR-5903Z support signal detect squelch, and how does it behave?
Yes, the AFBR-5903Z implements a hardware signal detect (SD) squelch function. When optical input power falls to −45 dBm or lower, SD deasserts (goes to PECL low), forcing RD+ and RD− outputs to steady PECL high and low states respectively. SD asserts (PECL high) when input rises to −33 dBm or higher, restoring normal data output. The hysteresis is 1.5–2.4 dB, and deassertion time (ANSMax) is guaranteed ≤350 µs, making AFBR-5903Z suitable for deterministic loss-of-signal detection in FDDI and ATM systems.
What are the key differences between AFBR-5903Z and AFBR-5903EZ?
The AFBR-5903Z and AFBR-5903EZ share identical optical, electrical, and thermal specifications-including 0°C to +70°C operation, −34.5 dBm receiver sensitivity, and +3.3 V supply-but differ mechanically: AFBR-5903EZ includes an extended internal EMI shield over the receiver subassembly and conductive housing, while AFBR-5903Z has no shield. Both use the same 2×5 MT-RJ package and pinout, but AFBR-5903EZ is preferred in high-noise environments where enhanced immunity to external EMI fields is required.
Can the AFBR-5903Z be used in IEEE 802.3u 100BASE-FX applications?
Yes, the AFBR-5903Z is fully compliant with IEEE 802.3u 100BASE-FX because the Fast Ethernet Alliance defines its Physical Layer for 100BASE-FX as identical to the FDDI PMD standard (ISO/IEC 9314-3). Its optical output power (−15.7 dBm BOL), receiver sensitivity (−34.5 dBm), and 125 MBd signaling rate meet all 100BASE-FX requirements for 2 km multimode fiber links. The AFBR-5903Z has been validated for use in Fast Ethernet uplinks and aggregation ports where standards conformance and link margin are critical.
What termination and decoupling is required for AFBR-5903Z PECL interfaces?
The AFBR-5903Z requires external 50 Ω terminations for all differential PECL signals: RD+/RD− and TD+/TD− must each be terminated to +3.3 V via 50 Ω resistors, and 130 Ω/82 Ω resistor networks are recommended per Figure 7. Receiver and transmitter supplies (VCC RX/VCC TX) need local decoupling: 10 µF bulk + 10 nF ceramic capacitors placed adjacent to pins 2 and 6, plus 1 µH RF chokes. A continuous ground plane under the device and isolated solder posts tied to chassis ground are mandatory for signal integrity and EMI control in AFBR-5903Z designs.
AFBR-5903Z Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Broadcom Limited
- Series:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Data Rate:
- 100Mbps
- Wavelength:
- 1300nm
- Applications:
- General Purpose
- Voltage - Supply:
- 3.3V
- Connector Type:
- MTRJ
- Mounting Type:
- Through Hole
AFBR-5903Z FAQ
1.How can I place an order for AFBR-5903Z through Aetrix?
Please submit a Request for Quotation (RFQ) for AFBR-5903Z on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AFBR-5903Z reliable?
The price and inventory of AFBR-5903Z are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AFBR-5903Z is usually 5 days.
3.What payment methods are accepted for AFBR-5903Z?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AFBR-5903Z transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AFBR-5903Z?
AFBR-5903Z orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AFBR-5903Z order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AFBR-5903Z?
For technical support, including AFBR-5903Z datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AFBR-5903Z requirements.
6.How does Aetrix verify that AFBR-5903Z is sourced from the original manufacturer or authorized distributors?
All AFBR-5903Z products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AFBR-5903Z meets industry standards.
7.What is the process for return or replacement of AFBR-5903Z?
All AFBR-5903Z units undergo pre-shipment inspection (PSI). If there is an issue with AFBR-5903Z, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AFBR-5903Z part is unused and in its original packaging.
Return procedure for AFBR-5903Z:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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