Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Optoelectronics > Fiber Optic Transceiver Modules

Broadcom Limited AFBR-89CDHZ

Name: AFBR-89CDHZ
Brand: Broadcom Limited
SKU: AFBR-89CDHZ
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: AFBR-89CDHZ

Manufacturer:: Broadcom Limited

Category:: Fiber Optic Transceiver Modules

Package:

Datasheet:: AFBR-89CDHZ.pdf

Description:: TXRX QSFP28 100GBPS 850NM

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,134

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

The AFBR-89CDHZ from Broadcom is a four-channel, pluggable QSFP28 multimode fiber optic transceiver for 100 Gigabit Ethernet applications. It operates at 25.78125 Gb/s per lane over 850 nm VCSEL/PIN technology, delivers 103.125 Gb/s aggregate bandwidth, supports up to 100 m on OM4 fiber, and uses a 38-pin edge connector with MPO optical interface - deployed in datacenter switch interconnects requiring high-density, hot-pluggable 100GbE links.

For engineers reviewing the AFBR-89CDHZ datasheet, pinout, applications, or equivalent options, key selection considerations include IEEE 802.3bm Clause 91 RS-FEC compliance, 0°C to +70°C case temperature operation, integrated digital diagnostics (temperature, supply voltage, TX bias, RX input power), Class 1 laser safety, and QSFP28 MSA SFF-8636 Rev 2.9 conformance.

Technical Context

The AFBR-89CDHZ implements a parallel 4×25.78125 Gb/s CAUI-4 electrical interface compliant with IEEE 802.3bm Annex 83E and Clause 91 RS-FEC, with per-lane CML I/O, internal AC coupling, and 100 Ω differential termination on TX side. It integrates Broadcom VCSEL transmitter and PIN receiver arrays with on-die retimers that can be bypassed for alternate data rates.

Its two-wire serial (TWS) interface provides LVTTL-compatible SCL/SDA control, real-time monitoring of module temperature (Page 00h, Addr 22–23), +3.3 V supply (Addr 26–27), per-channel TX output power (Addr 50–57), TX bias current (Addr 42–49), and RX input power (Addr 34–41), all with configurable alarm/warning thresholds and latched interrupt flags.

Key Specifications

Parameter	Value and Actual Design Meaning
Form Factor	QSFP28 per SFF-8636 Rev 2.9 and SFF-8661 mechanical spec - ensures interoperability with standard cages and host board layouts.
Data Rate per Lane	25.78125 Gb/s with 256b/257b encoding - enables full 100GBASE-SR4 compliance and 103.125 Gb/s aggregate bandwidth.
Optical Interface	8-fiber or 12-fiber MPO connector, 850 nm SR4 - supports plug-and-play deployment on OM3 (70 m) and OM4 (100 m) multimode fiber.
Electrical Interface	38-contact edge connector, CML I/O, 100 Ω differential - eliminates need for external AC coupling capacitors or terminations on host board.
Operating Temperature	0°C to +70°C case temperature - validated for enterprise datacenter switch/router front-panel environments.
Power Consumption	Max 2.5 W (Power Class 3) - fits thermal envelope of high-port-count QSFP28 line cards without forced airflow derating.
Laser Safety	IEC 60825-1 / CDRH Class 1 - no user-accessible hazardous radiation under normal or single-fault conditions.
Diagnostics	Real-time TWS-readable values for temp, Vcc, per-channel TX bias, TX output power, RX input power - enables predictive link health monitoring and fault isolation.

Pinout & Package

Package: QSFP28-compliant metal housing with shielded design per SFF-8661, 18.35 mm × 72.2 mm × 8.5 mm (W × L × H), Class 1 laser-rated enclosure.

Pin/Terminal	Circuit Role	Design Meaning
1, 4, 7, 13, 16, 19, 20, 23, 26, 32, 35, 38	GND	Signal ground common to all analog/digital circuits - 12 dedicated pins ensure low-impedance return path for high-speed lanes and power domains.
10, 29, 30	VccRx / VccTx / Vcc1	Separate +3.3 V supplies for receiver, transmitter, and logic - enables independent power sequencing and noise isolation between analog blocks.
2–3, 5–6, 33–34, 36–37	TX2n/p, TX4n/p, TX3n/p, TX1n/p	Differential CML inputs for 4 transmit lanes - AC-coupled internally; host must provide 100 Ω differential termination only on ASIC side.
14–15, 17–18, 21–22, 24–25	RX3p/n, RX1p/n, RX2p/n, RX4p/n	Differential CML outputs for 4 receive lanes - terminated at host ASIC; module provides 100 Ω differential load on TX side only.
8, 9, 11–12, 27–28, 31	ModSelL, ResetL, SCL, SDA, ModPrsL, IntL, LPMode	LVTTL/LVCMOS control signals - enable hot-plug detection, reset, diagnostics polling, interrupt notification, and low-power mode entry without host firmware changes.

Key Features

Feature	Design Value
RS-FEC support per IEEE 802.3 Clause 91	Enables robust 100GBASE-SR4 operation over 100 m OM4 with 1.5 dB total connection loss budget - no host SerDes FEC required.
Integrated digital diagnostics	Provides per-channel TX bias, TX output power, RX input power, plus module temp and Vcc - allows real-time link margin assessment and predictive failure analysis.
Push-pull tab mechanical design	Reduces insertion/extraction force by >30% vs. standard QSFP28 levers - critical for high-density chassis with >32 ports per line card.
Hot-pluggable operation	Supports live insertion/removal without host power cycle - maintains system uptime during field upgrades or link repairs.
Class 1 eye safety certification	Validated per IEC 60825-1 Ed. 3 and CDRH 21 CFR 1040.10 - eliminates need for user-accessible warning labels or administrative controls in end equipment.
Shielded metal housing	Meets FCC Part 15 / EN55022 Class B EMI limits without host board shielding - simplifies system-level EMC validation.

Applications

Datacenter Switch Interconnect	High-Density Router Uplink
Use Scenario: 100GbE leaf-spine fabric links between top-of-rack and aggregation switches using OM4 MMF. IC Role / Device Role / Timing Role: Pluggable optical transceiver providing parallel 4×25.78125 Gb/s electrical-to-optical conversion with embedded RS-FEC. Use Value: Enables 100 Gb/s per port at <2.5 W power, supports 100 m reach, and integrates diagnostics for automated link health reporting via host I²C.	Use Scenario: Core router line card uplinks to datacenter interconnect (DCI) gateways over short-reach multimode fiber. IC Role / Device Role / Timing Role: Hot-pluggable QSFP28 SR4 module handling full-duplex 100GBASE-SR4 traffic with deterministic latency and jitter performance. Use Value: Delivers sub-100 ns optical path latency, meets IEEE 802.3bm stressed receiver mask requirements, and supports push-pull extraction in constrained front-panel layouts.
Enterprise Storage Network	Hyperscale Server Aggregation
Use Scenario: Fibre Channel over Ethernet (FCoE) or iSCSI storage fabric connecting servers to SAN switches. IC Role / Device Role / Timing Role: Optical interface bridging server NICs and storage switch ports with guaranteed BER <10⁻¹² under RS-FEC correction. Use Value: Provides deterministic error correction via Clause 91 RS-FEC, supports OM3/OM4 backward compatibility, and reports per-lane RX optical power for cable plant verification.	Use Scenario: Rack-scale server-to-TOR switch connectivity in AI/ML training clusters requiring ultra-low-latency 100 Gb/s links. IC Role / Device Role / Timing Role: High-reliability parallel fiber transceiver with proven Broadcom VCSEL/PIN technology and 85 °C storage rating. Use Value: Achieves >1 million hours MTBF, supports 0–70 °C case temp operation, and includes latched interrupt flags for rapid LOS/fault detection without host polling.

Datacenter Switch Interconnect

High-Density Router Uplink

Use Scenario: 100GbE leaf-spine fabric links between top-of-rack and aggregation switches using OM4 MMF.

IC Role / Device Role / Timing Role: Pluggable optical transceiver providing parallel 4×25.78125 Gb/s electrical-to-optical conversion with embedded RS-FEC.

Use Value: Enables 100 Gb/s per port at <2.5 W power, supports 100 m reach, and integrates diagnostics for automated link health reporting via host I²C.

Use Scenario: Core router line card uplinks to datacenter interconnect (DCI) gateways over short-reach multimode fiber.

IC Role / Device Role / Timing Role: Hot-pluggable QSFP28 SR4 module handling full-duplex 100GBASE-SR4 traffic with deterministic latency and jitter performance.

Use Value: Delivers sub-100 ns optical path latency, meets IEEE 802.3bm stressed receiver mask requirements, and supports push-pull extraction in constrained front-panel layouts.

Enterprise Storage Network

Hyperscale Server Aggregation

Use Scenario: Fibre Channel over Ethernet (FCoE) or iSCSI storage fabric connecting servers to SAN switches.

IC Role / Device Role / Timing Role: Optical interface bridging server NICs and storage switch ports with guaranteed BER <10⁻¹² under RS-FEC correction.

Use Value: Provides deterministic error correction via Clause 91 RS-FEC, supports OM3/OM4 backward compatibility, and reports per-lane RX optical power for cable plant verification.

Use Scenario: Rack-scale server-to-TOR switch connectivity in AI/ML training clusters requiring ultra-low-latency 100 Gb/s links.

IC Role / Device Role / Timing Role: High-reliability parallel fiber transceiver with proven Broadcom VCSEL/PIN technology and 85 °C storage rating.

Use Value: Achieves >1 million hours MTBF, supports 0–70 °C case temp operation, and includes latched interrupt flags for rapid LOS/fault detection without host polling.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 100GbE SR4 transceiver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AFBR-89CDPZ	Same optical/electrical specs but uses non-shielded plastic housing - lower EMI suppression and no Class 1 certification documentation.	Not suitable for FCC/CE-regulated equipment without additional chassis-level shielding.	Select AFBR-89CDHZ when regulatory compliance (FCC/EN55022) and Class 1 laser safety are mandatory.
Finisar FTLC9555REPM	Identical QSFP28 SR4 form factor and 100GBASE-SR4 performance, but uses different VCSEL array vendor and lacks Broadcom-specific diagnostic register mapping.	Requires host firmware adaptation for TWS register access; same OM4 100 m reach and 25.78125 Gb/s lane rate.	Choose FTLC9555REPM only if existing Finisar driver stack is already deployed and diagnostic granularity is secondary.

Compared with AFBR-89CDPZ and FTLC9555REPM, the AFBR-89CDHZ uniquely combines certified Class 1 laser safety, shielded metal housing for out-of-the-box EMI compliance, and Broadcom-native diagnostic register layout - making it the preferred choice for carrier-grade and regulated enterprise systems where certification traceability and signal integrity are non-negotiable.

Availability

AFBR-89CDHZ is available at Aetrix Electronics and suitable for datacenter switch interconnects, high-density router uplinks, and enterprise storage networks requiring stable component supply, long-term lifecycle support, and full regulatory documentation including UL, RoHS, and laser safety certifications.

Supply support for AFBR-89CDHZ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Broadcom Inc. is a global semiconductor leader designing and supplying infrastructure software and silicon solutions for networking, storage, and broadband markets.

The AFBR-89CDHZ belongs to Broadcom's AFBR QSFP28 transceiver product line, engineered specifically for standards-compliant, high-reliability 100GbE short-reach optical interconnects in cloud-scale and telecom infrastructure.

FAQ

What is the maximum supported fiber distance for AFBR-89CDHZ on OM4 cable?

The AFBR-89CDHZ supports up to 100 meters on OM4 multimode fiber, as defined in IEEE 802.3bm Clause 95 for 100GBASE-SR4 operation. This distance assumes ≤1.5 dB total connection and splice loss, with individual connections not exceeding 0.75 dB. The AFBR-89CDHZ achieves this using 850 nm VCSELs and RS-FEC correction, and its optical specifications - including average launch power (–8.4 to +2.4 dBm per lane) and stressed receiver sensitivity (–5.2 dBm OMA) - are fully validated to meet this reach.

Does AFBR-89CDHZ require external AC coupling capacitors on the host board?

No, the AFBR-89CDHZ integrates AC coupling capacitors internally for both transmitter inputs and receiver outputs. Host board design requires only 100 Ω differential termination on the receiver-side ASIC/SerDes; no external capacitors or termination resistors are needed on the module interface traces. This simplifies PCB layout, reduces bill-of-materials cost, and improves signal integrity consistency across production units - a key advantage confirmed in the AFBR-89CDHZ datasheet Section "High-Speed Electrical Signal Interface".

How does the digital diagnostic monitoring in AFBR-89CDHZ support predictive maintenance?

The AFBR-89CDHZ provides real-time, TWS-accessible monitoring of module temperature, +3.3 V supply voltage, per-channel TX bias current, TX output power, and RX input power - all with programmable alarm/warning thresholds and latched interrupt flags. By trending these parameters (e.g., rising TX bias at constant output power), operators can detect early laser degradation before link errors occur. This capability, documented in the "Digital Diagnostic Monitoring" section of the AFBR-89CDHZ datasheet, enables predictive failure identification and minimizes unplanned downtime in mission-critical 100GbE infrastructure.

Is AFBR-89CDHZ compatible with standard QSFP28 cages and host board layouts?

Yes, the AFBR-89CDHZ complies fully with the QSFP28 Multi-Source Agreement (MSA) SFF-8636 Rev 2.9 and mechanical specification SFF-8661. Its 38-pin edge connector, 18.35 mm × 72.2 mm × 8.5 mm package outline, and pinout (including GND placement, power pin allocation, and CML/LVTTL signal assignments) match the MSA baseline - ensuring drop-in compatibility with industry-standard cages, thermal solutions, and PCB footprints. This compliance is explicitly verified in the "Package Outline" and "QSFP28 Transceiver Pin Layout" sections of the AFBR-89CDHZ datasheet.

What safety certifications apply to AFBR-89CDHZ?

The AFBR-89CDHZ is certified as a Class 1 Laser Product per IEC 60825-1 Ed. 3 and 21 CFR 1040.10 (CDRH), with TÜV file R 72201311 and CB file US-TUVR-012148. It also carries UL/CSA Component Recognition (UL File E484615), RoHS compliance (<1000 ppm restricted substances), and meets FCC Part 15 / EN55022 Class B EMI limits. These certifications are listed in the "Regulatory Compliance Table" of the AFBR-89CDHZ-DS103 datasheet and are enabled by its shielded metal housing and optically enclosed VCSEL/PIN architecture.

AFBR-89CDHZ Specifications

Product attributes: Attribute value

Manufacturer:: Broadcom Limited

Series:: -

Packaging:: Tray

Product Status:: Obsolete

Data Rate:: 100Gbps

Wavelength:: 850nm

Applications:: Ethernet, Telecom/Datacom Systems

Voltage - Supply:: 3.3V

Connector Type:: MTP® (MPO)

Mounting Type:: Pluggable, QSFP28

AFBR-89CDHZ FAQ

1.How can I place an order for AFBR-89CDHZ through Aetrix?

Please submit a Request for Quotation (RFQ) for AFBR-89CDHZ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AFBR-89CDHZ reliable?

The price and inventory of AFBR-89CDHZ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AFBR-89CDHZ is usually 5 days.

3.What payment methods are accepted for AFBR-89CDHZ?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AFBR-89CDHZ transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AFBR-89CDHZ?

AFBR-89CDHZ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AFBR-89CDHZ order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AFBR-89CDHZ?

For technical support, including AFBR-89CDHZ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AFBR-89CDHZ requirements.

6.How does Aetrix verify that AFBR-89CDHZ is sourced from the original manufacturer or authorized distributors?

All AFBR-89CDHZ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AFBR-89CDHZ meets industry standards.

7.What is the process for return or replacement of AFBR-89CDHZ?

All AFBR-89CDHZ units undergo pre-shipment inspection (PSI). If there is an issue with AFBR-89CDHZ, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AFBR-89CDHZ part is unused and in its original packaging.

Return procedure for AFBR-89CDHZ:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-10 Schmitt Trigger Explained: Hysteresis, Circuits, Inverters and Applications

Schmitt triggers use separate rising and falling thresholds to stabilize slow or noisy signals. This guide covers hysteresis, 74HC14 and 74HCT14 selection, comparator calculations, RC oscillators and p…

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…