Texas Instruments AFE7728DIABJ
- Part No.:
- AFE7728DIABJ
- Manufacturer:
- Texas Instruments
- Category:
- RF Transceiver ICs
- Package:
- 400-BFBGA, FCBGA
- Datasheet:
-
AFE7728DIABJ.pdf
- Description:
- IC RF TXRX+MCU CELLULAR 400FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AFE7728DIABJ from Texas Instruments is a dual-channel RF transceiver with integrated CFR/DPD engine, designed for 4G/5G base station feedback paths and PA linearization. It features two 0-IF TX chains (up to 650 MHz DPD expansion BW), two 0-IF RX chains (up to 200 MHz received IBW), and two direct RF-sampling feedback paths (650 MHz observed bandwidth), operating across 600 MHz–6 GHz. Used in macro RRU and mMIMO active antenna systems.
For engineers reviewing the AFE7728DIABJ datasheet, AFE7728DIABJ pinout, AFE7728DIABJ application, or AFE7728DIABJ equivalent, key selection criteria include JESD204C SerDes support (29.5 Gbps), dual-band LO synthesis via four fractional-N PLLs, GaN-optimized DPD correction, smart data capture capability, and FCBGA-400 package compatibility with thermal and layout constraints in high-density RRU designs.
Technical Context
The AFE7728DIABJ implements a dual-transmitter/dual-receiver architecture with two independent RF-sampling feedback ADCs, each supporting up to 650 MHz DPD expansion bandwidth and equipped with dual NCOs for rapid band switching. Its hardware-accelerated DPD estimator uses signal dynamics modeling specifically for GaN PA memory effects, while the multistage CFR unit applies configurable cancelling pulses to reduce PAR before transmission.
Each TX chain integrates two 14-bit, 3.3-Gsps DACs, programmable reconstruction filters, IQ modulators, and 39-dB analog gain control; each RX chain includes a 28-dB digital step attenuator, passive IQ demodulator, antialiasing LPF, and continuous-time sigma-delta ADCs - all calibrated via on-chip QMC and LO leakage cancellation leveraging feedback path data.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| RF Frequency Range | 600 MHz to 6 GHz - supports global 4G/5G FR1 bands including n7, n41, n78, and n102 without external up/down-conversion. |
| TX Instantaneous BW | Up to 650 MHz per chain - enables wideband DPD model training and correction for multi-carrier 5G NR signals. |
| RX Instantaneous BW | Up to 200 MHz per chain - captures full 100-MHz 5G NR channel plus guard bands for accurate AGC and monitoring. |
| Feedback Path BW | Up to 650 MHz observed bandwidth - allows real-time observation of PA distortion across entire transmit spectrum for adaptive DPD update. |
| JESD204C Speed | Up to 29.5 Gbps per SerDes lane - reduces lane count vs. JESD204B, easing FPGA interface design and PCB routing density. |
| PLL Architecture | Four fractional-N RF PLLs + one integer-N DC PLL - supports dual-band operation (e.g., 2.6 GHz + 3.5 GHz) with independent LO generation per chain. |
| Package | FCBGA-400 (ABJ), 17 mm × 17 mm, 0.8-mm pitch - qualified for industrial temperature range (–40°C to +85°C) with MSL-3 rating. |
Pinout & Package
AFE7728DIABJ is housed in a 17-mm × 17-mm FCBGA package with 400 solder balls, 0.8-mm pitch, and 2.65-mm maximum height. The package supports thermal dissipation via exposed die paddle and is compatible with standard JEDEC tray handling (90 units/tray).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TXA_P/N, TXC_P/N | Differential TX analog output | Direct RF output pairs for two independent transmitter chains; require 50-Ω matched routing to PA input. |
| RXA_P/N, RXC_P/N | Differential RX analog input | Baseband IQ inputs for two receiver chains; accept 0-IF signals from external demodulators or direct antenna coupling. |
| FB_P/N | Differential feedback ADC input | Direct RF sampling input for observed signal capture; supports up to 650 MHz bandwidth with internal DSA and 14-bit ADC. |
| CLK_P/N, SYSREF_P/N | JESD204C timing reference | Provides device clock and deterministic latency alignment signal for multi-device synchronization (Subclass 1). |
| VDD1P8TX, VDD1P2TX | TX chain power supplies | Separate 1.8-V and 1.2-V rails isolate noise-sensitive DAC and modulator sections from digital logic domains. |
| SPI bus pins (F_SPI, GPIO) | Configuration & control interface | 4-wire SPI with frame sync enables register programming of DPD coefficients, QMC settings, and PLL configurations. |
Key Features
| Feature | Design Value |
|---|---|
| GaN-optimized DPD corrector | Compensates long-term memory effects from charge trapping in GaN PAs using signal dynamics modeling - improves ACLR by ≥8 dB over legacy DPD. |
| Smart data capture | Selectively samples feedback data at critical intercept points (e.g., PA input/output) to reduce FPGA memory bandwidth by up to 60% during DPD training. |
| On-chip QMC & LO leakage cancellation | Real-time correction of I/Q imbalance and LO feedthrough in TX/RX chains without external calibration tones or offline processing. |
| Dual-band LO synthesis | Four independent fractional-N PLLs enable simultaneous dual-frequency operation (e.g., 2.6 GHz + 3.5 GHz) with <100-fs integrated jitter per LO. |
| JESD204C 64b/66b encoding | Reduces overhead vs. 8b/10b, increasing effective throughput by 20% at same SerDes rate - lowers FPGA resource utilization for data framing. |
Applications
| Macro Remote Radio Unit (RRU) | Small Cell Base Station |
|---|---|
|
Use Scenario: High-power outdoor RRU serving multiple sectors with 100-MHz 5G NR carriers and massive MIMO beamforming. IC Role / Device Role / Timing Role: Dual TX/RX + dual FB path enables concurrent transmission, reception, and real-time DPD adaptation for two independent antenna arrays. Use Value: Integrated DPD engine eliminates need for external FPGA-based linearization, reducing BOM cost and board area by 35% vs. discrete solutions. |
Use Scenario: Indoor/outdoor small cell deploying 2×2 MIMO with carrier aggregation across 1.8 GHz and 2.6 GHz bands. IC Role / Device Role / Timing Role: Dual-band LO synthesis and JESD204C interface allow single AFE7728DIABJ to drive two independent RF front-ends with deterministic latency alignment. Use Value: 29.5-Gbps SerDes lanes reduce interconnect count by 50% compared to JESD204B-based alternatives, simplifying FPGA pinout and PCB layer count. |
| Active Antenna System (AAS) | Distributed Antenna System (DAS) |
|
Use Scenario: mMIMO base station with 64T64R active antenna array requiring compact, low-power transceiver per TRX module. IC Role / Device Role / Timing Role: High channel density (2 TX + 2 RX + 2 FB) in single FCBGA-400 package replaces two legacy quad-channel ICs, cutting footprint by 40%. Use Value: Integrated CFR reduces peak-to-average ratio by 4–6 dB, enabling higher PA efficiency and lower thermal load in sealed AAS enclosures. |
Use Scenario: Multi-operator DAS head-end unit aggregating signals from multiple carriers and frequency bands into shared fiber distribution. IC Role / Device Role / Timing Role: Wide 600 MHz–6 GHz tuning range and programmable RX/TX filters support reconfiguration across LTE, NR, and private 5G bands without hardware change. Use Value: On-chip digital step attenuators (28 dB range) and RF overload detectors enable autonomous AGC across varying input levels from diverse donor sources. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AFE7768DIABJ | Quad-channel variant (4 TX + 4 RX + 2 FB); identical DPD engine, PLL architecture, and JESD204C support. | Targets 64T64R mMIMO AAS where higher channel count per chip reduces system-level IC count and interconnect complexity. | Select AFE7768DIABJ when scaling beyond dual-chain requirements while retaining pin compatibility and firmware reuse. |
| AD9082BBCZ | Quad-DAC/quad-ADC with 2 FB paths; supports up to 2.4 GHz instantaneous bandwidth but lacks integrated GaN-optimized DPD engine. | Requires external FPGA or processor for DPD estimation/correction, increasing latency and system-level design effort. | Choose AD9082BBCZ only if wider instantaneous bandwidth (>200 MHz) is prioritized over integrated DPD acceleration and GaN-specific correction. |
Compared with AFE7728DIABJ, AFE7768DIABJ offers double the channel count in the same package footprint and pinout, while AD9082BBCZ provides broader instantaneous bandwidth but shifts DPD implementation burden to external logic - making AFE7728DIABJ optimal for cost- and latency-sensitive 2T2R RRU and small cell deployments.
Availability
AFE7728DIABJ is available at Aetrix Electronics and suitable for macro RRU, small cell base stations, and active antenna systems requiring stable component supply, industrial temperature operation (–40°C to +85°C), and long-term lifecycle assurance.
Supply support for AFE7728DIABJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in high-performance RF, power management, and signal chain technologies.
The AFE77xxD family targets wireless infrastructure applications, specifically engineered to integrate transceiver, feedback, and DPD functions into a single chip for 4G/5G base station radios - reducing size, power, and system complexity.
FAQ
What is the RF frequency coverage of the AFE7728DIABJ?
The AFE7728DIABJ operates from 600 MHz to 6 GHz, covering all major 4G LTE and 5G NR frequency bands including n7 (2.5–2.69 GHz), n41 (2.496–2.69 GHz), n78 (3.3–3.8 GHz), and n102 (4.4–5.0 GHz). This range enables single-device deployment across macro, small cell, and indoor RAN architectures without external frequency translation stages.
Does the AFE7728DIABJ support JESD204C and what benefits does it provide?
Yes, the AFE7728DIABJ supports JESD204C at up to 29.5 Gbps per lane with 64b/66b encoding. This reduces protocol overhead by ~20% versus JESD204B's 8b/10b, increases effective data throughput, lowers FPGA logic utilization for link layer handling, and enables deterministic latency synchronization (Subclass 1) across multi-device systems like mMIMO antenna arrays.
How does the integrated DPD engine in the AFE7728DIABJ differ from generic DPD implementations?
The AFE7728DIABJ integrates a hardware-accelerated DPD estimator with signal dynamics modeling specifically tuned for GaN PA memory effects, including charge trapping compensation. Unlike generic FPGA-based DPD, this on-chip engine delivers sub-microsecond adaptation latency, eliminates external compute resources, and achieves ≥8 dB ACLR improvement on 100-MHz 5G NR signals without host processor intervention.
What is the role of the feedback (FB) paths in the AFE7728DIABJ?
The AFE7728DIABJ includes two dedicated RF-sampling feedback paths, each with a 14-bit, 3.3-Gsps ADC and input DSA, supporting up to 650 MHz observed bandwidth. These paths capture PA output distortion in real time for adaptive DPD coefficient updates, enable QMC/LO leakage calibration using TX signal leakage, and support smart data capture to reduce FPGA memory bandwidth during training cycles.
Is the AFE7728DIABJ pin-compatible with other devices in the AFE77xxD family?
Yes, the AFE7728DIABJ is pin-compatible with AFE7768DIABJ and AFE7769DIABJ within the same ABJ (FCBGA-400) package. All share identical ball map, power sequencing, and JESD204C interface layout - enabling hardware reuse across dual-channel (AFE7728D), quad-channel (AFE7768D), and extended-bandwidth (AFE7769D) variants with only firmware and configuration changes required.
AFE7728DIABJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 400-BFBGA, FCBGA
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Type:
- TxRx + MCU
- RF Family/Standard:
- Cellular
- Protocol:
- -
- Modulation:
- -
- Frequency:
- 600MHz ~ 6GHz
- Data Rate (Max):
- 29.5Gbps
- Power - Output:
- -
- Sensitivity:
- -
- Memory Size:
- -
- Serial Interfaces:
- GPIO, SPI
- GPIO:
- -
- Voltage - Supply:
- -
- Current - Receiving:
- -
- Current - Transmitting:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 400-FCBGA (17x17)
AFE7728DIABJ FAQ
1.How can I place an order for AFE7728DIABJ through Aetrix?
Please submit a Request for Quotation (RFQ) for AFE7728DIABJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AFE7728DIABJ reliable?
The price and inventory of AFE7728DIABJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AFE7728DIABJ is usually 5 days.
3.What payment methods are accepted for AFE7728DIABJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AFE7728DIABJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AFE7728DIABJ?
AFE7728DIABJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AFE7728DIABJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AFE7728DIABJ?
For technical support, including AFE7728DIABJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AFE7728DIABJ requirements.
6.How does Aetrix verify that AFE7728DIABJ is sourced from the original manufacturer or authorized distributors?
All AFE7728DIABJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AFE7728DIABJ meets industry standards.
7.What is the process for return or replacement of AFE7728DIABJ?
All AFE7728DIABJ units undergo pre-shipment inspection (PSI). If there is an issue with AFE7728DIABJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AFE7728DIABJ part is unused and in its original packaging.
Return procedure for AFE7728DIABJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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