Texas Instruments AFE8190IAMJ
- Part No.:
- AFE8190IAMJ
- Manufacturer:
- Texas Instruments
- Category:
- RF Transceiver ICs
- Package:
- 784-BFBGA, FCBGA
- Datasheet:
-
AFE8190IAMJ.pdf
- Description:
- 16-CHANNEL RF-SAMPLING TRANSCEIV
- Quantity:
- Payment:

- Shipping:

Inventory:3,847
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AFE8190IAMJ from Texas Instruments is a 16-channel RF transceiver IC integrating sixteen 12GSPS transmit DACs, sixteen 5GSPS receive ADCs, and four 5GSPS feedback ADCs, supporting up to 7.2GHz RF frequency range and 800MHz TX/FB bandwidth - deployed in macro remote radio units and mMIMO active antenna systems.
For engineers reviewing the AFE8190IAMJ datasheet, AFE8190IAMJ pinout, AFE8190IAMJ application, or AFE8190IAMJ equivalent, key selection considerations include JESD204C interface support (32.5Gbps), integrated PLL/VCO clock generation, 784-ball FCBGA package with 0.8mm pitch, and TDD operation with fast TX/RX switching for 5G base station signal chains.
Technical Context
The AFE8190IAMJ implements independent digital up/down converters per channel: DUCs enable 800MHz TX signal bandwidth with mixed-mode DAC output, while DDCs deliver 600MHz RX bandwidth. Each chain includes dedicated DSAs - 39dB TX (1dB analog + 0.125dB digital steps), 30dB RX (1dB step), and 25dB FB (1dB step).
It supports JESD204B/C subclass 1 synchronization across 16 SerDes lanes at up to 32.5Gbps, with 8b/10b and 64b/66b encoding, and operates with internal PLL/VCO or optional external clock at DAC/ADC rates - enabling precise multi-device timing alignment in distributed 5G infrastructure.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| TX DAC Sampling Rate | 12 GSPS - enables direct RF synthesis up to 7.2GHz without analog upconversion stages |
| RX ADC Sampling Rate | 5 GSPS - supports wideband 5G NR carrier aggregation with 600MHz real-time bandwidth |
| Feedback ADC Rate | 5 GSPS × 4 channels - provides high-fidelity digital predistortion (DPD) correction paths |
| RF Frequency Range | DC to 7.2 GHz - covers sub-6GHz 5G bands including n77/n78/n79 and legacy 4G LTE bands |
| Digital Interface | JESD204C (32.5Gbps) - reduces SerDes lane count vs JESD204B for same throughput, easing PCB routing |
| DSA Resolution | TX: 0.125dB digital + 1dB analog steps - allows fine-grained closed-loop gain control for DPD convergence |
| Package | FCBGA-784, 23mm × 23mm, 0.8mm pitch - requires controlled-depth solder paste and thermal via design for RF performance stability |
Pinout & Package
AFE8190IAMJ uses a 784-ball flip-chip ball grid array (FCBGA) package, 23mm × 23mm, 0.8mm pitch, with 2.751mm max height and exposed thermal pad. Ball A1 marked by chamfered corner; pin 1 identification per JEDEC MO-271 standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A28, B1–B28, ..., AH1–AH28 | High-speed SerDes lanes (JESD204C) | 16 bidirectional transceivers supporting 32.5Gbps; require matched-length differential routing and AC coupling |
| E1–E28, F1–F28, ..., U1–U28 | Analog supply (AVDD_TX, AVDD_RX, AVDD_FB) | Multiple isolated 1.0V/1.8V domains - each requires local low-ESR decoupling and separate power planes |
| G1–G28, H1–H28, ..., T1–T28 | Ground balls (GND) | 784-ball layout includes >200 dedicated ground balls for EMI suppression and return path integrity |
| V1–V28, W1–W28, ..., AH1–AH28 | Digital I/O (SPI, GPIO, CLK, RESET) | SPI interface (4-wire) for configuration; GPIOs support TDD mode control and status reporting |
| Center thermal pad | Thermal & electrical ground | Exposed metal pad must be soldered to internal ground plane with ≥6 thermal vias for junction temperature control |
Key Features
| Feature | Design Value |
|---|---|
| TDD fast-switching architecture | Enables <1μs TX-to-RX transition for time-division duplex 5G NR frames without external switch control logic |
| Mixed-mode DAC output | Supports 2nd Nyquist zone operation - eliminates need for image-reject filters in direct-conversion architectures |
| On-chip peak & power detectors | Each RX chain includes analog/digital peak detectors and RF overload protection - reduces FPGA resource load for AGC implementation |
| Subclass 1 JESD204C sync | Ensures deterministic latency and multi-device phase alignment across up to 16 AFE8190IAMJ devices in mMIMO arrays |
| Integrated PLL/VCO | Generates all DAC/ADC clocks from single reference input - eliminates external clock synthesizer and reduces jitter-sensitive BOM count |
Applications
| Macro Remote Radio Unit (RRU) | Active Antenna System (AAS) mMIMO |
|---|---|
Use Scenario: High-power outdoor base station unit connecting to centralized BBU via CPRI/eCPRI over fiber. IC Role / Device Role / Timing Role: Primary RF transceiver handling 16× dual-polarized antenna elements with integrated DPD feedback paths. Use Value: Eliminates discrete DAC/ADC/DSA components - reduces board area by >40% and simplifies thermal management in sealed RRU enclosures. | Use Scenario: Indoor/outdoor mMIMO base station with 64–128 antenna elements using beamforming and massive MIMO processing. IC Role / Device Role / Timing Role: Channelized RF front-end for 16-element subarrays, synchronized via JESD204C subclass 1 across multiple AFE8190IAMJ devices. Use Value: Enables real-time DPD per subarray using quad feedback ADCs - improves ACLR by ≥12dB over legacy architectures. |
| Small Cell Base Station | Distributed Antenna System (DAS) |
Use Scenario: Low-power urban cell site deployed on lampposts or building façades with limited cooling and space. IC Role / Device Role / Timing Role: Full-duplex transceiver supporting TDD 5G NR with dynamic spectrum sharing (DSS) between 4G/5G. Use Value: Internal PLL/VCO and fast TDD switching allow single-clock-domain operation - removes need for external clock buffers and reduces component count by 7+ parts. | Use Scenario: In-building coverage solution distributing RF signals from donor source to multiple remote antenna nodes via coaxial/fiber. IC Role / Device Role / Timing Role: Remote node transceiver converting digital baseband to RF and vice versa, with embedded DSA for automatic gain leveling across long cable runs. Use Value: 30dB RX DSA with 1dB steps maintains consistent SNR across ±15dB path loss variation - eliminates manual calibration during DAS commissioning. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF transceiver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AFE7900IABJ | 8-channel (vs 16), 12GSPS TX/5GSPS RX, no integrated feedback ADCs - requires external feedback path design | Targeted for mid-tier small cells and repeaters where channel count and DPD complexity are lower | Select when system needs ≤8 channels and can implement external feedback ADCs for cost-sensitive deployments |
| AD9081BBCZ | 8-channel (vs 16), 12GSPS TX/6GSPS RX, integrated DPD engine - lacks quad feedback ADCs but includes on-die DPD accelerator | Optimized for FPGA-based DPD offload in compact form factor; less suitable for pure analog feedback loop implementations | Select when FPGA resources are constrained and on-chip DPD acceleration is preferred over analog feedback path fidelity |
Compared with AFE7900IABJ and AD9081BBCZ, the AFE8190IAMJ uniquely delivers 16-channel density with integrated quad 5GSPS feedback ADCs - making it the only option for high-channel-count mMIMO systems requiring analog-domain DPD correction without external ADCs or FPGA logic overhead.
Availability
AFE8190IAMJ is available at Aetrix Electronics and suitable for macro RRU, mMIMO AAS, and small cell base station designs requiring stable component supply, full production traceability, and long-term lifecycle support.
Supply support for AFE8190IAMJ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in high-speed data converters and RF signal chain products.
The AFE8190IAMJ belongs to TI's AFE8xxx family of wideband RF transceivers, designed specifically for 5G wireless infrastructure - emphasizing channel density, integrated DPD support, and JESD204C scalability in macro and mMIMO base stations.
FAQ
What is the maximum RF signal bandwidth supported by the AFE8190IAMJ in transmit mode?
The AFE8190IAMJ supports a maximum RF signal bandwidth of 800MHz in transmit mode, enabled by its 12GSPS DACs and single DUC per chain. This bandwidth accommodates wideband 5G NR carriers, including contiguous 100MHz+ allocations in n77/n78 bands. The 800MHz TX bandwidth is verified in the SBASAM4 datasheet Section 1 and applies directly to the AFE8190IAMJ device under specified operating conditions.
Does the AFE8190IAMJ include integrated digital up/down converters (DUC/DDC)?
Yes, the AFE8190IAMJ integrates one DUC per transmit chain and one DDC per receive chain. Each DUC supports up to 800MHz signal bandwidth, and each DDC supports up to 600MHz bandwidth. These are hard-macro blocks implemented in the device silicon - confirmed in the functional block diagram and Section 3 description of the SBASAM4 datasheet for AFE8190IAMJ.
What package type and ball count does the AFE8190IAMJ use?
The AFE8190IAMJ uses a 784-ball flip-chip ball grid array (FCBGA) package designated AMJ, with 23mm × 23mm body size and 0.8mm ball pitch. This is documented in the "Mechanical, Packaging, and Orderable Information" section (Section 6) of the SBASAM4 datasheet and confirmed in TI's packaging addendum for AFE8190IAMJ.
Can the AFE8190IAMJ operate in time-division duplex (TDD) mode?
Yes, the AFE8190IAMJ supports TDD operation with fast switching between transmit and receive modes - enabling sub-microsecond transitions required for 5G NR TDD frame structures. This capability is explicitly listed in the Features section of the SBASAM4 datasheet and applies to the AFE8190IAMJ without external circuitry.
What JESD204 interface versions does the AFE8190IAMJ support?
The AFE8190IAMJ supports both JESD204B and JESD204C standards, with SerDes transceivers capable of up to 32.5Gbps per lane. It implements subclass 1 for deterministic latency and multi-device synchronization - a requirement for mMIMO beamforming coherence. This dual-standard support is specified in the "Digital Data Interface" subsection of the SBASAM4 datasheet for AFE8190IAMJ.
Is an external clock required for AFE8190IAMJ operation, or does it include an on-chip PLL/VCO?
The AFE8190IAMJ includes an internal PLL/VCO to generate DAC and ADC sampling clocks from a single reference input - eliminating the need for external clock synthesizers in most configurations. An optional external clock at DAC or ADC rate is supported, but not required. This is confirmed in the Features and Description sections of the SBASAM4 datasheet for AFE8190IAMJ.
AFE8190IAMJ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 784-BFBGA, FCBGA
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- -
- Type:
- TxRx + MCU
- RF Family/Standard:
- Non-Standard
- Protocol:
- -
- Modulation:
- -
- Frequency:
- 7.2GHz
- Data Rate (Max):
- 32.5Gbps
- Power - Output:
- -
- Sensitivity:
- -
- Memory Size:
- -
- Serial Interfaces:
- GPIO, SPI
- GPIO:
- -
- Voltage - Supply:
- -
- Current - Receiving:
- -
- Current - Transmitting:
- -
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 784-FCBGA (23x23)
AFE8190IAMJ FAQ
1.How can I place an order for AFE8190IAMJ through Aetrix?
Please submit a Request for Quotation (RFQ) for AFE8190IAMJ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AFE8190IAMJ reliable?
The price and inventory of AFE8190IAMJ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AFE8190IAMJ is usually 5 days.
3.What payment methods are accepted for AFE8190IAMJ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AFE8190IAMJ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AFE8190IAMJ?
AFE8190IAMJ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AFE8190IAMJ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AFE8190IAMJ?
For technical support, including AFE8190IAMJ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AFE8190IAMJ requirements.
6.How does Aetrix verify that AFE8190IAMJ is sourced from the original manufacturer or authorized distributors?
All AFE8190IAMJ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AFE8190IAMJ meets industry standards.
7.What is the process for return or replacement of AFE8190IAMJ?
All AFE8190IAMJ units undergo pre-shipment inspection (PSI). If there is an issue with AFE8190IAMJ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AFE8190IAMJ part is unused and in its original packaging.
Return procedure for AFE8190IAMJ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AFE8190IAMJ Tags

-
ESP32-D0WD-V3
Espressif Systems

-
ESP8266EX
Espressif Systems

-
ESP32-S3
Espressif Systems

-
NRF24L01P-R7
Nordic Semiconductor ASA

-
NRF24L01P-R
Nordic Semiconductor ASA

-
ESP32-U4WDH
Espressif Systems

-
DA14531-00000OG2
Renesas

-
ESP32-C6FH4
Espressif Systems

-
DA14531-00000FX2
Renesas

-
NRF24L01P-T
Nordic Semiconductor ASA

-
NRF52810-QCAA-R
Nordic Semiconductor ASA

-
ESP32-S3FN8
Espressif Systems
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
