Asahi Kasei Microdevices/AKM AK1572

Overview

AK1572 from AsahiKASEI is a highly integrated down-converter mixer with fractional-N frequency synthesizer and triple-band VCO, designed for high-linearity RF-to-IF conversion in microwave radio links and cellular base stations. It supports RF input from 690 MHz to 4000 MHz, IF output from 20 MHz to 1000 MHz, and internal LO generation from 262.5 MHz to 4400 MHz. The device operates with 4.75–5.25 V for the mixer and 2.7–3.6 V or 4.75–5.25 V for the synthesizer/VCO, consuming 150 mA typ. at full operation.

For engineers reviewing the AK1572 datasheet, AK1572 pinout, AK1572 application, or AK1572 equivalent, key selection considerations include its dual-mode LO interface (internal VCO output or external LO injection), programmable charge pump current (CP1/CP2), fast lock timing control, VCO band calibration register ({VCO[1:0]}), and digital/analog lock detect configuration - all critical for stable PLL settling and system-level spectral purity in wireless infrastructure designs.

Technical Context

The AK1572 integrates a passive double-balanced mixer core, a 3-band VCO with automatic band calibration, a 24-bit fractional-N synthesizer using ΣΔ (AX) modulation, and a fully configurable phase-frequency detector (PFD) with 1.2–40 MHz operating range. Its loop architecture supports external loop filter design via CP output and VCNT control voltage, enabling precise phase noise optimization.

Operation modes are defined by PDN pin state and four register-controlled bits ({MODE[1:0]}, {MIXEN}, {DIV[1:0]}, {VCO[1:0]}), allowing independent activation of mixer, synthesizer, and VCO blocks - e.g., Func4 enables full down-conversion with internal LO output, while Func5 supports external LO injection with synthesizer-only PLL lock.

Key Specifications

Pinout & Package

AK1572 is housed in a thermally enhanced 32-pin QFN package (5 mm × 5 mm × 0.85 mm, 0.5 mm pitch) with exposed thermal pad requiring solder connection to PCB ground plane per MS1551-E-01 Section 19.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar down-converter mixer + synthesizer applications.

Compared with HMC8192LP6CE and ADRF6612, AK1572 uniquely combines fractional-N synthesis, triple-band VCO, and high-linearity mixer in one die - eliminating external PLL components while supporting both IF-sampling and superheterodyne architectures across 690–4000 MHz.

Availability

AK1572 is available at Aetrix Electronics and suitable for microwave radio link deployments, cellular base station transceivers, and repeater systems requiring stable component supply, long-term lifecycle support, and traceable sourcing for telecom infrastructure programs.

Supply support for AK1572 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

AsahiKASEI Microdevices Corporation (formerly AKM Semiconductor) is a Japanese semiconductor company specializing in high-performance analog and mixed-signal ICs for communications, audio, and sensor applications.

The AK1572 belongs to AsahiKASEI's RF front-end product line, engineered specifically for wireless infrastructure applications demanding high linearity, low phase noise, and flexible LO architecture in compact form factors.

FAQ

What is the recommended power-up sequence for AK1572?

The AK1572 requires strict sequencing: (1) assert PDN low while applying all supplies (VDD1/VDD2/VDD3); (2) wait ≥10 ms for VREF1 LDO stabilization; (3) write all registers (0x01–0x04); (4) raise PDN high; (5) wait ≥500 μs for internal bias stabilization; then (6) write Address 0x01 to trigger VCO calibration and PLL lock. Skipping step (5) risks calibration failure and unstable LO output in AK1572.

How does AK1572 handle VCO band selection during frequency tuning?

The AK1572 performs automatic VCO band calibration upon writing Address 0x01, using the {VCO[1:0]} register value to constrain the search space among three overlapping bands (2.1–3.0 GHz, 3.0–3.4 GHz, 3.4–4.4 GHz). Calibration disconnects VCNT from the loop filter and applies an internal reference to ensure accurate band selection - a process controlled by {CALTM[3:0]} to balance precision and time. This ensures optimal phase noise and K_VCO for each target frequency in AK1572.

Can AK1572 operate with an external LO instead of its internal VCO?

Yes - AK1572 supports external LO injection via the LOP/LON pins when {MODE[1:0]} = 3 (Func6) or {MODE[1:0]} = 2 (Func2). In Func6, only the mixer is active; in Func2, the synthesizer remains active for PLL locking to the external LO. The device accepts differential LO inputs up to +12 dBm and provides 100 Ω termination. This mode bypasses the internal VCO entirely, making AK1572 adaptable to systems with legacy LO sources or multi-chip synchronization requirements.

What determines the lock detect behavior in AK1572?

Lock detection in AK1572 is configured by the {LD} bit in Address 0x04: when LD = 0, digital lock detect uses an on-chip counter (set via {LDCNTSEL}) to validate phase error < T for N consecutive cycles; when LD = 1, analog lock detect outputs raw PFD phase error directly on the LD pin. The unlocked-to-locked threshold (N = 15 or 31) and locked-to-unlocked threshold (N = 3 or 7) are independently programmable. This dual-mode flexibility allows system designers to optimize between jitter immunity and response speed in AK1572-based PLLs.

How is current consumption adjusted in AK1572?

AK1572 current consumption is adjusted via two external resistors: a 33 kΩ resistor on MIXBIAS sets mixer bias current (affecting conversion gain and NF), and a 27 kΩ resistor on CPBIAS sets charge pump current scale (I_CP = 8.1 μA / R). Register bits CP1[2:0] and CP2[2:0] then multiply this base current by (CP1+1) or (CP2+1) to yield final charge pump values from 245 μA to 2945 μA. This dual-resistor scheme enables independent optimization of analog performance and PLL dynamics in AK1572.