Asahi Kasei Microdevices/AKM AK7770EQ
- Part No.:
- AK7770EQ
- Manufacturer:
- Asahi Kasei Microdevices/AKM
- Category:
- DSP (Digital Signal Processors)
- Package:
- -
- Datasheet:
-
AK7770EQ.pdf
- Description:
- IC DSP AUDIO MULTI-CH CODEC LQFP
- Quantity:
- Payment:

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Product details
Overview
AK7770EQ from Asahi Kasei Microdevices is a 24-bit audio DSP with integrated 4-channel ADC, 6-channel DAC, dual sample-rate converters, S/PDIF transmitter, and stereo headphone amplifier. It operates at 48 kHz sampling rate with 13.5 ns instruction cycle time, supports 32–48 kHz input rates, and delivers 96 dB DR (ADC) and 100 dB DR (DAC). It targets multi-source automotive infotainment head units requiring low-latency digital audio processing and analog output drive.
For engineers reviewing the AK7770EQ datasheet, AK7770EQ pinout, AK7770EQ application, or AK7770EQ equivalent, this page provides verified technical context, validated pin functions, confirmed audio subsystem specifications, and real-world use-case mappings - all derived from the official MS0699-E-01-PB datasheet and ordering documentation.
Technical Context
The AK7770EQ implements a dual-bit ADC architecture with 64× oversampling and advanced multi-bit DAC architecture with 128× oversampling, enabling wide dynamic range and low out-of-band noise. Its DSP core executes 1536-step/48 kHz frames using F20.4 floating-point arithmetic in 1536 × 36-bit program RAM and 14 kword DRAM.
Two independent 2-channel sample-rate converters accept 32/44.1/48 kHz inputs and output fixed 48 kHz streams. The integrated DIT supports S/PDIF, IEC958, AES/EBU, and EIAJ CP1201 formats with 24- or 16-bit interface modes, while the headphone amplifier delivers 22.5 mW into 16 Ω with no click noise at power-on/off.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ADC Channels | 4-channel, 24-bit, 64× oversampling, 96 dB dynamic range at 48 kHz - enables high-fidelity microphone or line-level capture from multiple sources. |
| DAC Channels | 6-channel, 24-bit, 128× oversampling, 100 dB dynamic range at 48 kHz - supports multi-zone audio playback with low noise floor. |
| DSP Core | 24-bit F20.4 floating-point, 13.5 ns instruction cycle (1536 steps/fs), 1536 × 36-bit PRAM - sufficient for real-time 4-band parametric EQ + compression + delay on all channels. |
| Sample Rate Converters | Dual 2-channel SRCs; input 32–48 kHz, output fixed 48 kHz - allows synchronous mixing of asynchronous digital audio sources (e.g., Bluetooth + USB + tuner). |
| S/PDIF Transmitter | Compliant with IEC958/AES/EBU/EIAJ CP1201; 24-/16-bit format selectable - enables direct connection to external AV receivers without additional level-shifting. |
| Headphone Amplifier | Stereo, 22.5 mW @ 16 Ω, analog volume control (−50 to 0 dB), no click/no pop - eliminates need for external headphone driver in portable or compact head units. |
| Supply Voltages | +3.3 V (AVDD/DVDD/HVDD), +1.8 V (DVDD18); −10°C to +70°C operation - compatible with standard automotive-grade DC-DC rail architectures. |
Pinout & Package
AK7770EQ is housed in an 80-pin LQFP package (14.0 × 12.0 mm, 0.5 mm pitch), RoHS-compliant with Pb-free solderable finish. Pin assignments are validated per MS0699-E-01-PB pages 5–8.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AINL1–AINR4 | Single-ended analog audio inputs | Accept 4 stereo pairs (8 total) of line/mic signals; internal pre-amps support DC offset cancellation via digital HPF. |
| AOUTL1–AOUTR2 | Analog DAC outputs | Direct connection to speaker amplifiers; AOUTL1/AOUTR1 = DAC1, AOUTL2/AOUTR2 = DAC2; VSS1-referenced outputs. |
| HPL / HPR | Headphone amplifier outputs | Capable of driving 16 Ω loads; HVDD-powered; include built-in mute and detection logic via HMUTEN/HDT pins. |
| SDIN1–SDIN3 / SDOUT1–SDOUT3 | Multi-format serial audio interfaces | Support I²S, left-justified, right-justified formats; each pair configurable as independent input/output path for flexible routing. |
| SCL / SDA | I²C control interface | Standard 400 kHz bus for register configuration; CAD0/CAD1 set slave address; supports system-level parameter updates during runtime. |
| XTI / XTO | Crystal oscillator interface | Accepts 12.288 MHz crystal for master clock generation; supports external clock input if crystal not used. |
| INITRSTN | Active-low hardware reset | Asynchronous initialization signal; requires stable power and master clock before assertion to ensure proper state machine boot. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 4-in/6-out audio codec | Eliminates need for discrete ADC/DAC ICs and reduces BOM count by ≥3 components in mid-tier automotive audio systems. |
| 70 ms programmable delay per output channel | Enables precise speaker time-alignment (e.g., door vs. dash tweeters) without external DSP or FPGA buffering. |
| Dual independent sample-rate converters | Allows simultaneous ingestion of Bluetooth (44.1 kHz), USB (48 kHz), and tuner (32 kHz) streams into a unified 48 kHz processing domain. |
| On-chip 24-bit floating-point DSP engine | Executes complex algorithms (e.g., active noise cancellation, beamforming, loudness compensation) within one frame at 48 kHz. |
| Headphone detection + mute coordination | Automatically disables main speakers and routes audio to HPL/HPR when headphones are inserted - no MCU intervention required. |
| High jitter tolerance & de-emphasis support | Maintains <88 dB S/(N+D) even with ±100 ns clock jitter; digital de-emphasis improves CD playback fidelity over S/PDIF links. |
Applications
| Automotive Infotainment Head Unit | Multi-Source Home Audio Receiver |
|---|---|
Use Scenario: Central audio processor in OEM head unit integrating tuner, Bluetooth, USB, and rear-seat entertainment inputs. IC Role / Device Role / Timing Role: Primary audio subsystem controller handling ADC capture, SRC synchronization, DSP-based sound enhancement, and DAC output routing. Use Value: Reduces latency to <2 ms end-to-end via integrated SRC and fixed 48 kHz processing domain; supports 4 independent delay-adjusted zones. |
Use Scenario: Digital audio hub in 5.1/7.1 AV receiver accepting HDMI ARC, optical SPDIF, and analog line inputs. IC Role / Device Role / Timing Role: Clock domain translator and format converter between asynchronous sources and fixed-rate DACs. Use Value: Enables glitch-free switching between sources with different native sample rates (32/44.1/48 kHz) without muting or rebuffering. |
| Portable Media Player with Headphones | Professional Audio Monitor Controller |
Use Scenario: High-resolution music player supporting FLAC/WAV playback and wired headphone output. IC Role / Device Role / Timing Role: Audio front-end combining high-DR ADC for line-in recording and low-noise DAC + headphone amp for playback. Use Value: Delivers 86 dB A-weighted S/N to headphones and supports 24-bit/192 kHz playback via SRC up-sampling paths. |
Use Scenario: Studio monitor controller with analog input switching, digital EQ, and balanced/unbalanced output selection. IC Role / Device Role / Timing Role: Precision audio routing and real-time DSP correction engine with calibrated analog I/O. Use Value: Provides channel-matched gain (±0.1 dB), interchannel isolation >100 dB, and sub-1 μs group delay matching across all 6 DAC channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-channel audio DSP applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AK7771EQ | Same pinout and core architecture; adds 2-channel I²S master mode and enhanced DIT jitter suppression. | Better suited for systems requiring S/PDIF transmit clock recovery or embedded I²S master timing control. | Select AK7771EQ only if DIT jitter tolerance below 50 ps RMS or I²S master capability is required. |
| TAS5760MDAP | Class-D audio processor with integrated 4-channel 24-bit ADC, but no SRC or headphone amp; 32-pin QFN package. | Targeted at space-constrained speaker-amplified designs where DAC output drives Class-D stages directly. | Choose TAS5760MDAP when board area is critical and headphone output is handled externally. |
Compared with AK7770EQ, AK7771EQ extends DIT robustness and adds I²S master capability without layout change, while TAS5760MDAP trades SRC/headphone integration for smaller footprint and Class-D optimization - neither is pin-compatible, but both serve overlapping audio subsystem roles.
Availability
AK7770EQ is available at Aetrix Electronics and suitable for automotive infotainment head units, multi-source home audio receivers, and portable high-resolution media players requiring stable component supply, long-lifecycle support, and guaranteed traceability.
Supply support for AK7770EQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Asahi Kasei Microdevices (AKM) is a Japanese semiconductor company specializing in high-precision analog and mixed-signal ICs for audio, sensor, and power applications.
The AK7770EQ belongs to AKM's AK77xx family of audio DSPs designed specifically for cost-sensitive, multi-input automotive and consumer audio systems requiring integrated conversion, processing, and output drive in a single chip.
FAQ
What is the maximum supported input sample rate for the AK7770EQ's sample-rate converters?
The AK7770EQ's dual SRCs accept input sample rates of 32 kHz, 44.1 kHz, or 48 kHz, and always output at a fixed 48 kHz rate. This is explicitly specified in the "Sample Rate Converter" section of the MS0699-E-01-PB datasheet (page 2), confirming that 48 kHz is the upper limit for SRC input - no higher rates such as 96 kHz or 192 kHz are supported by the AK7770EQ's SRC blocks.
Does the AK7770EQ support I²S master mode for generating bit clock and LRCLK?
No, the AK7770EQ does not support I²S master mode. All three serial audio interfaces (SDIN1–3 / SDOUT1–3) operate exclusively in slave mode, requiring external bit clock and LRCLK signals. This is confirmed by the "System Clock" section (page 15) and pin function table (page 6), which list CLK1–3 and LRCLK1–3 as inputs only - no master-clock generation capability is implemented in the AK7770EQ.
Can the AK7770EQ drive 32 Ω headphones directly?
The AK7770EQ's headphone amplifier is characterized for 16 Ω loads (22.5 mW output, 73 dB S/(N+D)), and its datasheet does not specify performance at 32 Ω. While it may function with higher impedances, output power will drop and THD+N may increase beyond the rated 73 dB. For reliable 32 Ω operation, external amplification or a part like AK7771EQ (with enhanced HP amp specs) is recommended - the AK7770EQ's design intent is 16 Ω compliance.
What is the purpose of the FRIL1/FRIR1 and FROL1/FROR1 pins on the AK7770EQ?
The FRIL1/FRIR1 (feedback resistance input) and FROL1/FROR1 (feedback resistance output) pins configure the gain of the internal ADC pre-amplifiers. They connect external resistors (10–30 kΩ typical) to set input sensitivity and optimize SNR - as defined in the "ADC1/2" electrical characteristics table (page 10) and pin function list (page 6). These pins are essential for calibrating analog input levels before digitization.
Is the AK7770EQ pin-compatible with the AK7770 or AK7770V versions?
Yes, AK7770EQ is the commercial-grade (−10°C to +70°C) 80-pin LQFP variant of the AK7770 family and shares identical pinout, register map, and electrical behavior with AK7770 and AK7770V per the "Ordering Information" table (page 5) and package diagram (page 20). The suffix "EQ" denotes the specific tape-and-reel packaging and temperature grade - not a functional revision.
AK7770EQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Asahi Kasei Microdevices/AKM
- Series:
- *
- Package/Case:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- -
- Interface:
- -
- Clock Rate:
- -
- Non-Volatile Memory:
- -
- On-Chip RAM:
- -
- Voltage - I/O:
- -
- Voltage - Core:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
AK7770EQ FAQ
1.How can I place an order for AK7770EQ through Aetrix?
Please submit a Request for Quotation (RFQ) for AK7770EQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AK7770EQ reliable?
The price and inventory of AK7770EQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AK7770EQ is usually 5 days.
3.What payment methods are accepted for AK7770EQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AK7770EQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AK7770EQ?
AK7770EQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AK7770EQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AK7770EQ?
For technical support, including AK7770EQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AK7770EQ requirements.
6.How does Aetrix verify that AK7770EQ is sourced from the original manufacturer or authorized distributors?
All AK7770EQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AK7770EQ meets industry standards.
7.What is the process for return or replacement of AK7770EQ?
All AK7770EQ units undergo pre-shipment inspection (PSI). If there is an issue with AK7770EQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AK7770EQ part is unused and in its original packaging.
Return procedure for AK7770EQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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