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Asahi Kasei Microdevices/AKM AK8135F

Part No.:
AK8135F
Manufacturer:
Asahi Kasei Microdevices/AKM
Category:
Clock Generators, PLLs, Frequency Synthesizers
Package:
-
Datasheet:
AetrixAK8135F.pdf
Description:
INTEGRATED CIRCUIT
Quantity:
Payment:
Payment
Shipping:
Shipping

Inventory:3,473

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Product details

Overview

AK8135F from Asahi Kasei Microdevices (AKM) is a low-power, multi-output clock generator IC with integrated VCFS for precise frequency tuning. It accepts a 24.576 MHz crystal input and delivers seven synchronized outputs: CLK1 (24.576 MHz), CLK2 (24.99972 MHz), CLK3 (33.332965 MHz), and four 27.000 MHz reference outputs (REF1–REF4), all operating at 3.3 V with ±85 ppm VCFS pull range and 150 ps typical period jitter. It targets high-accuracy timing in digital video recorders and broadcast equipment.

For engineers reviewing the AK8135F datasheet, AK8135F pinout, AK8135F application, or AK8135F equivalent, key selection criteria include its dual VCFS architecture, 30-pin VSOP package compatibility, low 24 mA typical supply current at 3.3 V, 72 dB typical C/N on REF outputs, and support for system-level clock synchronization via analog voltage control inputs VIN1/VIN2.

Technical Context

The AK8135F integrates two independent Voltage Controlled Frequency Synthesizers (VCFS1 and VCFS2), each driven by dedicated analog control inputs (VIN1 and VIN2), enabling fine-grained ±85 ppm tuning of four 27.000 MHz outputs (REF1–REF4) while maintaining low jitter. Its architecture separates VCFS paths from the primary PLL-based CLK1–CLK3 generation, allowing independent enable/disable control via REF1PD and REF34PD pins.

Each output is assigned to a specific internal circuit block: CLK1 derives directly from the crystal oscillator via 1:1 division; CLK2 and CLK3 use PLL-based fractional synthesis (1/12 and 1/16 ratios per Figure 1); REF1–REF4 are generated exclusively by VCFS1 (REF1, REF2) and VCFS2 (REF3, REF4), with power-down capability and mode-select logic tied to digital control pins.

Key Specifications

Parameter Value and Actual Design Meaning
Supply Voltage3.0–3.6 V - Requires single-source supply to all six VDD pins; decoupling capacitors mandatory per pin for stable low-jitter operation.
Crystal Input24.576 MHz - Fixed-frequency fundamental-mode crystal connected across XI (Pin 3) and XO (Pin 1); CL = 10 pF recommended.
Output FrequenciesCLK1: 24.576 MHz; CLK2: 24.99972 MHz; CLK3: 33.332965 MHz; REF1–REF4: 27.000 MHz - All outputs simultaneously active under full-enable configuration.
VCFS Pull Range±85 ppm (typ.) - Achieved via 0.5VDD ±1.0 V analog control on VIN1/VIN2; enables real-time synchronization to external master clocks.
Period Jitter150 ps (typ.) - Measured at all outputs (CLK1–CLK3, REF1–REF4) under specified load conditions; critical for HDMI, SATA, and AV signal integrity.
C/N Ratio72 dB (typ.) - Measured on REF1–REF4 with 25 pF load; indicates low phase noise suitable for high-definition video timing.
Operating Temp−20 °C to +85 °C - Validated across industrial temperature range; supports deployment in STB and recorder chassis without forced cooling.

Pinout & Package

AK8135F is housed in a lead-free 30-pin Very Small Outline Package (VSOP), optimized for compact PCB layouts in space-constrained consumer electronics. The package features six VDD and seven GND pins distributed across the perimeter to minimize power-ground loop inductance and suppress supply noise coupling into sensitive clock paths.

Pin/Terminal Circuit Role Design Meaning
1: XOClock OutputCrystal oscillator output terminal; connects to one side of 24.576 MHz crystal; requires matched trace length to XI (Pin 3).
3: XIClock InputCrystal oscillator input terminal; connects to other side of 24.576 MHz crystal; forms resonant tank with XO and external load capacitors.
5: CLK1Output24.576 MHz reference clock; direct buffered crystal output; used for audio codec or USB PHY timing.
14: CLK2Output24.99972 MHz clock; PLL-derived output; commonly used for MPEG transport stream timing in DTVs.
15: CLK3Output33.332965 MHz clock; PLL-derived output; matches SMPTE 292/259 video line rate requirements.
20: REF2Output27.000 MHz VCFS1 output; enabled when REF1PD = H; used for HDMI pixel clock or video DAC sampling.
23: REF1Output27.000 MHz VCFS1 output; controlled by REF1PD pin; provides redundant 27 MHz source for system redundancy.
27: VIN2Analog InputVCFS2 control voltage input; accepts 0.5VDD ±1.0 V DC to tune REF3/REF4 frequency within ±85 ppm window.
28: VIN1Analog InputVCFS1 control voltage input; independently tunes REF1/REF2; allows differential VCFS calibration.
6: REF1PDDigital InputREF1 enable/disable control; "H" = 27 MHz output, "L" = logic-low output; internal 52 kΩ pull-up ensures safe default state.
19: REF34PDDigital InputREF3/REF4 and VCFS2 power-down control; "H" = active 27 MHz outputs and VCFS2 enabled; "L" = outputs forced low and VCFS2 powered down.

Key Features

Feature Design Value
Dual Independent VCFS BlocksSeparate VIN1/VIN2 inputs and REF1–REF2 / REF3–REF4 outputs allow simultaneous but independent frequency tuning of two 27 MHz domains for multi-channel sync.
Low-Jitter Output Architecture150 ps typical period jitter across all outputs ensures compliance with HDMI 1.4, SATA II, and SD-SDI timing budgets without external jitter cleaners.
Configurable Output Enable LogicREF1PD and REF34PD pins provide hardware-level output gating-enabling dynamic power reduction (e.g., disabling unused REF outputs saves ~7 mA per group).
Multi-Rail Power DistributionSix isolated VDD pins (VDD1–VDD6) and seven GND pins (GND1–GND7) reduce supply crosstalk between PLL, VCFS, and output buffers for consistent jitter performance.
Crystal-Referenced Accuracy±30 ppm output accuracy (at REF1–REF4) with 24.576 MHz crystal and 10 pF load capacitance-meets broadcast-grade timing stability for DTV and STB applications.

Applications

HDD/DVD/BD Recorder Digital Television (DTV)

Use Scenario: Simultaneous recording and playback of HD video streams with independent audio/video clock domains.

IC Role / Device Role / Timing Role: Multi-clock generator providing 24.576 MHz (audio), 27.000 MHz (video DAC), and 33.333 MHz (MPEG decoder) from single crystal.

Use Value: Eliminates need for multiple discrete oscillators; VCFS tuning aligns video clock to incoming broadcast timing reference, reducing frame buffer underrun.

Use Scenario: Real-time decoding and display of ATSC/QAM signals with strict jitter and skew requirements across HDMI, tuner, and demodulator subsystems.

IC Role / Device Role / Timing Role: Central timing hub delivering synchronized 24.576 MHz (audio PLL), 27.000 MHz (HDMI pixel clock), and 24.99972 MHz (transport stream clock).

Use Value: 72 dB C/N on REF outputs minimizes color noise in 1080p60 displays; dual VCFS allows independent tuning of HDMI and tuner clocks to match variable RF channel drift.

Set-Top Box (STB) Professional Video Capture

Use Scenario: Multi-tuner STB supporting concurrent recording, playback, and streaming with minimal board area and thermal footprint.

IC Role / Device Role / Timing Role: Low-power (24 mA typ.) clock source generating all required system clocks-including 27.000 MHz for video processing and 24.576 MHz for VoIP audio-within −20°C to +85°C ambient.

Use Value: Six VDD/GND pairs and 30-pin VSOP package enable dense layout near SoC; REF1PD/REF34PD enable dynamic power scaling during standby modes.

Use Scenario: Field-deployable 4K capture device requiring precise genlock to external house sync or tri-level reference.

IC Role / Device Role / Timing Role: Genlock-capable clock generator using VIN1/VIN2 to adjust REF1–REF4 frequency in real time based on phase error feedback from sync detector.

Use Value: ±85 ppm VCFS pull range accommodates standard broadcast sync tolerances; 400 ps long-term jitter meets SMPTE ST 2059-2 PTP timing stability requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-output clock generator applications.

Alternative Part Technical Difference Application Difference Selection Advice
AK8134FSingle VCFS (vs. dual), five outputs (vs. seven), no CLK2/CLK3 fractional synthesis - only REF1–REF4 + CLK1.Lacks independent tuning for dual video domains; insufficient for STBs requiring separate tuner and HDMI clocks.Select AK8134F only if system needs only one 27 MHz VCFS domain and omits 24.99972/33.332965 MHz outputs.
Si5332-A01A-GMProgrammable multi-synth (I²C-configurable), 12 outputs, ±0.1 ppb frequency resolution - no analog VCFS, higher power (65 mA).Requires firmware initialization; unsuitable for analog genlock; better for flexible clock tree synthesis than broadcast sync.Choose Si5332-A01A-GM when digital reconfiguration and ultra-fine frequency steps outweigh need for analog VCFS simplicity and low power.

Compared with AK8135F, AK8134F reduces cost and complexity for single-domain systems but sacrifices dual-VCFS flexibility and fractional clock outputs; Si5332-A01A-GM offers superior programmability and output count but demands I²C infrastructure and consumes nearly triple the current, making it less suitable for thermally constrained consumer enclosures.

Availability

AK8135F is available at Aetrix Electronics and suitable for HDD/DVD/BD recorders, digital televisions, and set-top boxes requiring stable component supply, industrial temperature operation, and analog genlock capability.

Supply support for AK8135F includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Asahi Kasei Microdevices Corporation (AKM) is a Japanese semiconductor company specializing in analog, mixed-signal, and sensor ICs, with leadership in audio codecs, Hall-effect sensors, and precision timing devices.

The AK8135F belongs to AKM's low-power multi-clock generator product line, designed specifically for broadcast and consumer video equipment where crystal-referenced accuracy, analog VCFS tuning, and multi-rail power integrity are essential for HDMI, SDI, and MPEG timing compliance.

FAQ

What is the function of the REF1PD and REF34PD pins on the AK8135F?

The REF1PD pin controls enable/disable of the REF1 output (27.000 MHz from VCFS1): logic high enables the output, logic low forces it low. The REF34PD pin simultaneously controls REF3, REF4, and powers down VCFS2. Both pins feature internal 52 kΩ pull-up resistors, ensuring safe default states. This design allows dynamic power management-disabling unused outputs reduces total current consumption by up to 8 mA, as confirmed in IDD3/IDD4 test conditions.

Does the AK8135F support genlock functionality, and how is it implemented?

Yes, the AK8135F supports analog genlock via its dual VCFS architecture. VIN1 (Pin 28) and VIN2 (Pin 27) accept external DC control voltages (0.5VDD ±1.0 V) to tune REF1–REF2 and REF3–REF4 frequencies within ±85 ppm of 27.000 MHz. This enables real-time alignment to external timing references such as tri-level sync or black burst signals. The typical VCFS pulling profile shown in Figure 4 confirms linear response across the control voltage range, making AK8135F suitable for professional video capture and broadcast equipment.

What are the recommended decoupling practices for the AK8135F's six VDD pins?

Each of the six VDD pins (VDD1–VDD6) must be decoupled with a 0.1 µF ceramic capacitor placed as close as possible to the respective pin, with the capacitor grounded to its corresponding GND pin (GND1–GND7). This practice is explicitly required in the Recommended Operating Conditions section to suppress supply noise coupling into PLL and VCFS blocks. Failure to follow this layout guideline risks increased period jitter beyond the specified 150 ps typical value, particularly on CLK2 and CLK3 outputs which rely on sensitive fractional synthesis.

Can the AK8135F generate the exact 25.000 MHz and 33.333 MHz frequencies listed in its datasheet?

The AK8135F outputs CLK2 at 24.99972 MHz and CLK3 at 33.332965 MHz-values intentionally offset from nominal 25.000 MHz and 33.333 MHz to avoid integer-related spurs and meet broadcast timing standards like ETSI EN 300 429. These frequencies are derived from the 24.576 MHz crystal via precise PLL division ratios (1/12 and 1/16 per Figure 1). The datasheet specifies output clock accuracy as ±30 ppm relative to target values under defined test conditions, confirming functional equivalence for MPEG transport and SD-SDI applications.

Is the AK8135F RoHS compliant, and what does the marking "Pb free" indicate?

Yes, the AK8135F is fully RoHS compliant and assembled in a lead-free package. Per AKM's official notice on page 11, all AKM integrated circuits in lead-free packages carry "Pb free" labeling on anti-static bags and shipping boxes. This designation confirms compliance with Directive 2011/65/EU and absence of lead, mercury, cadmium, hexavalent chromium, PBB, and PBDE above threshold limits-critical for export to EU, Japan, and China markets.

AK8135F Specifications

Product attributes
Attribute value
Manufacturer:
Asahi Kasei Microdevices/AKM
Series:
*
Package/Case:
-
Packaging:
Tape & Reel (TR)
Product Status:
Obsolete
Programmable:
Not Verified
Type:
-
PLL:
-
Input:
-
Output:
-
Number of Circuits:
-
Ratio - Input:Output:
-
Differential - Input:Output:
-
Frequency - Max:
-
Divider/Multiplier:
-
Voltage - Supply:
-
Operating Temperature:
-
Mounting Type:
-
Grade:
-
Qualification:
-
Supplier Device Package:
-

AK8135F FAQ

1.How can I place an order for AK8135F through Aetrix?

Please submit a Request for Quotation (RFQ) for AK8135F on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AK8135F reliable?

The price and inventory of AK8135F are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AK8135F is usually 5 days.

3.What payment methods are accepted for AK8135F?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AK8135F transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AK8135F?

AK8135F orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AK8135F order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AK8135F?

For technical support, including AK8135F datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AK8135F requirements.

6.How does Aetrix verify that AK8135F is sourced from the original manufacturer or authorized distributors?

All AK8135F products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AK8135F meets industry standards.

7.What is the process for return or replacement of AK8135F?

All AK8135F units undergo pre-shipment inspection (PSI). If there is an issue with AK8135F, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AK8135F part is unused and in its original packaging.

Return procedure for AK8135F:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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