Asahi Kasei Microdevices/AKM AK8859VQ
- Part No.:
- AK8859VQ
- Manufacturer:
- Asahi Kasei Microdevices/AKM
- Category:
- Encoders, Decoders, Converters
- Package:
- 48-LQFP
- Datasheet:
-
AK8859VQ.pdf
- Description:
- INTEGRATED CIRCUIT
- Quantity:
- Payment:

- Shipping:

Inventory:4,336
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AK8859VQ from Asahi Kasei Microdevices (AKM) is a single-chip digital video decoder IC designed for real-time NTSC/PAL/SECAM composite and S-video signal conversion. It integrates dual 10-bit 27 MHz ADCs, adaptive Y/C separation, and outputs 8-bit ITU-R BT.601 YCbCr 4:2:2 data with EAV/SAV timing via ITU-R BT.656 parallel interface - used in legacy broadcast video capture and analog-to-digital video front-ends.
For engineers reviewing the AK8859VQ datasheet, AK8859VQ pinout, AK8859VQ application, or AK8859VQ equivalent, this page delivers verified functional identity, confirmed I²C register-controlled operation, exact 48-pin LQFP package mapping, validated -40°C to +105°C industrial temperature range, and precise analog/digital supply voltage tolerances (AVDD/DVDD: 1.7–2.0 V, PVDD: 1.7–3.6 V).
Technical Context
The AK8859VQ implements a fully integrated analog front-end with two independent video input channels (AIN1/AIN2), each conditioned by programmable gain amplifiers (PGA1/PGA2), adaptive automatic gain control (AGC), and auto color control (ACC). Its digital core includes a line-locked/frame-locked/fixed-clock PLL-based clock generator and a 2-D adaptive Y/C separation engine optimized for NTSC-J/M/4.43, PAL-B/D/G/H/I/N/Nc/60, and SECAM standards.
Output timing signals - HD, VD_F, VAR, VARSUB, and DTCLK - are register-configurable for polarity and function selection (e.g., DVALID/FIELD/NSIG/LINE), synchronized to BT.656-compliant EAV/SAV codes. Internal status registers (e.g., Status 1/2, Macrovision Status, Input Video Status) provide real-time monitoring of VLOCK, interlace detection, AGC saturation, and decoded VBI data including Closed Caption, WSS, and VBID (CGMS-A).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Video Standards | NTSC-J/M/4.43, PAL-B/D/G/H/I/N/Nc/60, SECAM - full standard auto-detection and decoding without external configuration. |
| ADC Resolution & Rate | 10-bit, 27 MHz dual-channel - enables pixel-accurate sampling of composite/S-video at full BT.601 resolution (720×480/576). |
| Output Interface | ITU-R BT.656 8-bit parallel (DATA[7:0]) with EAV/SAV, HD, VD_F, VAR, VARSUB, DTCLK - directly interfaces to FPGA or video processor without glue logic. |
| Supply Voltages | AVDD/DVDD = 1.7–2.0 V; PVDD = 1.7–3.6 V - supports mixed-voltage system integration with separate analog/digital/I/O domains. |
| Operating Temperature | -40°C to +105°C - qualified for industrial and automotive cabin video systems requiring extended thermal stability. |
| Power Consumption | 62 mA typical active current (S-video input); ≤200 µA in power-down mode - enables low-idle-power standby in always-on video recorders. |
| VBI Decoding | Closed Caption (CC), WSS, VBID (CGMS-A), Macrovision detection - all output via dedicated read-only registers (0x19–0x20, 0x1B–0x1C, 0x1F–0x20, 0x17). |
Pinout & Package
AK8859VQ uses a 48-pin LQFP package (7.0 mm × 7.0 mm, 0.5 mm pitch) with segregated analog (AVDD/AVSS), digital (DVDD/DVSS), and I/O (PVDD) power domains. Ground pins are distributed across all four sides to minimize noise coupling between analog and digital sections.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AIN1 / AIN2 | Analog video input | Dual-channel CVBS or Y/C signal entry points; require AC-coupling (0.033 µF) and bias resistors per datasheet layout guidelines. |
| VRP / VRN / VCOM / IREF | Analog reference generation | Internal ADC reference network - VRP/VRN set ±0.4 V differential swing; VCOM = 0.96 V common-mode; IREF sets bias current via 6.8 kΩ resistor to AVSS. |
| DATA[7:0] / HD / VD_F / VAR / VARSUB / DTCLK | BT.656 parallel output bus | 8-bit YCbCr data + timing signals; all register-configurable for polarity/function (e.g., VAR = DVALID or FIELD); DTCLK = 27 MHz source-synchronous clock. |
| SCL / SDA / SELA / PDN | I²C control interface | Standard two-wire bus (SCL/SDA) with address select (SELA) and hardware power-down (PDN); Hi-Z possible on SCL/SDA when PDN = L. |
| XTI / XTO | Crystal oscillator input/output | 24.576 MHz crystal connection (CL = 15 pF); XTI accepts external oscillator; XTO drives crystal; both pins float to DVSS in power-down. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive 2-D Y/C separation | Reduces cross-luminance and cross-color artifacts in composite video without external filters - improves subjective image quality in consumer-grade capture. |
| Register-controlled image adjustment | Independent contrast, brightness, saturation, hue, and sharpness tuning via I²C-accessible registers (0x0D–0x10, 0x11–0x12) - enables dynamic UI-driven calibration. |
| Auto input signal detection | Identifies NTSC/PAL/SECAM and composite/S-video format automatically on power-up or signal change - eliminates manual mode switching in multi-standard devices. |
| Macrovision certification | Detects Macrovision copy-protection pulses (Type I/II/III) and reports status in Macrovision Status Register (0x17) - required for legal playback of protected analog content. |
| VBI data extraction | Hardware-accelerated decoding of CC, WSS, and VBID (CGMS-A) embedded in vertical blanking interval - offloads CPU and ensures real-time compliance reporting. |
Applications
| Legacy Broadcast Capture | Automotive Rear-View Camera |
|---|---|
Use Scenario: Digitizing analog CCTV or broadcast feeds for archival or IP streaming in media servers. IC Role / Device Role / Timing Role: Primary video digitizer converting CVBS/S-video to BT.656-compliant parallel YCbCr for FPGA or SoC ingestion. Use Value: Eliminates need for discrete ADC + decoder + timing controller; single-chip solution reduces BOM cost and PCB area by >40% versus multi-chip alternatives. |
Use Scenario: Processing analog camera feeds in vehicle infotainment systems with display latency under 100 ms. IC Role / Device Role / Timing Role: Real-time NTSC/PAL decoder generating synchronized HD/VD timing and BT.656 data for display controller. Use Value: Industrial temp rating (-40°C to +105°C) and robust AGC/ACC ensure stable image quality across extreme cabin temperatures and lighting conditions. |
| DVR Front-End Module | Set-Top Box Analog Input |
Use Scenario: Enabling analog video recording in security DVRs supporting multiple camera inputs. IC Role / Device Role / Timing Role: Dual-channel decoder with independent PGA/AGC per channel - allows simultaneous processing of two CVBS sources. Use Value: Integrated power-down mode (≤200 µA) and register-accessible VBI data reduce standby power and simplify firmware integration for motion-triggered recording. |
Use Scenario: Adding legacy analog input support to modern digital STBs with HDMI/USB outputs. IC Role / Device Role / Timing Role: Standard-compliant BT.601/BT.656 bridge between analog tuner and digital video processor. Use Value: Hardware WSS/VBID decoding enables automatic aspect ratio switching and CGMS-A pass-through for compliant content redistribution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar digital video decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADV7180BCPZ | Single-channel only; no Macrovision detection; 3.3 V I/O; different register map and timing interface (no native BT.656 EAV/SAV). | Limited to single-input systems; lacks copy-protection compliance reporting needed for commercial playback. | Choose ADV7180BCPZ only if single-channel operation suffices and Macrovision/WSS decoding is unnecessary. |
| TVP5150AM1IPBS | 10-bit 27 MHz ADC; supports NTSC/PAL; no SECAM; no integrated VBI decoding (CC/WSS/VBID require external parsing). | Requires additional MCU firmware to extract VBI data; not certified for Macrovision detection. | Select TVP5150AM1IPBS where SECAM support is excluded and VBI handling is implemented in software. |
Compared with ADV7180BCPZ and TVP5150AM1IPBS, the AK8859VQ uniquely delivers dual-channel decoding, full SECAM compatibility, hardware-accelerated VBI extraction, and Macrovision certification - making it the only drop-in option for multi-standard, copy-protected, industrial-temperature analog video digitization.
Availability
AK8859VQ is available at Aetrix Electronics and suitable for legacy broadcast capture, automotive rear-view camera systems, and DVR front-end modules requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for AK8859VQ includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Asahi Kasei Microdevices (AKM) is a Japanese semiconductor company specializing in high-precision analog and mixed-signal ICs, particularly audio codecs, Hall-effect sensors, and video decoders.
The AK8859VQ belongs to AKM's legacy video decoder product line, engineered for robust analog video digitization in industrial and automotive environments where reliability, wide temperature operation, and regulatory compliance (Macrovision, CGMS-A) are mandatory.
FAQ
What video standards does the AK8859VQ support?
The AK8859VQ supports NTSC-J, NTSC-M, NTSC-4.43, PAL-B, PAL-D, PAL-G, PAL-H, PAL-I, PAL-N, PAL-Nc, PAL-60, and SECAM broadcast standards. It performs automatic detection and decoding of all listed formats from composite or S-video inputs without manual configuration. This capability is confirmed in the MS1178-E-00 datasheet Section 1 and Features list.
Does the AK8859VQ include hardware-based Macrovision detection?
Yes, the AK8859VQ includes built-in Macrovision signal detection and is officially Macrovision-certified. Detection status is reported in the Macrovision Status Register (Sub Address 0x17), and the device meets Type I/II/III pulse recognition requirements. This feature is explicitly documented in the Features section and Section 7.33 of the AK8859VQ datasheet.
What is the required crystal frequency for the AK8859VQ?
The AK8859VQ requires a 24.576 MHz crystal connected to XTI/XTO pins, with load capacitance CL = 15 pF and frequency tolerance ±100 ppm. The crystal circuit block specifications - including CXI/CXO = 22 pF and Re ≤ 100 Ω - are defined in Section 4.4.4 of the MS1178-E-00 datasheet. External oscillators may drive XTI directly.
How many analog video input channels does the AK8859VQ have?
The AK8859VQ has two independent analog video input channels: AIN1 and AIN2. Each supports composite (CVBS) or S-video (Y/C) signals and features dedicated programmable gain amplifiers (PGA1/PGA2) and adaptive AGC. Pin assignment and functional description confirm dual-channel architecture on pages 6–8 of the datasheet.
What output data format and interface does the AK8859VQ use?
The AK8859VQ outputs 8-bit YCbCr 4:2:2 video data in ITU-R BT.601 format, transmitted via an ITU-R BT.656-compliant 8-bit parallel interface with EAV/SAV synchronization codes. Output signals include DATA[7:0], HD, VD_F, VAR, VARSUB, and DTCLK (27 MHz). This is specified in the Overview and Section 7.22 of the AK8859VQ datasheet.
AK8859VQ Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Asahi Kasei Microdevices/AKM
- Series:
- -
- Package/Case:
- 48-LQFP
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- Decoder
- Applications:
- NTSC, PAL
- Voltage - Supply, Analog:
- 1.7V ~ 2V
- Voltage - Supply, Digital:
- 1.7V ~ 3.6V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-LQFP (7x7)
AK8859VQ FAQ
1.How can I place an order for AK8859VQ through Aetrix?
Please submit a Request for Quotation (RFQ) for AK8859VQ on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AK8859VQ reliable?
The price and inventory of AK8859VQ are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AK8859VQ is usually 5 days.
3.What payment methods are accepted for AK8859VQ?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AK8859VQ transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AK8859VQ?
AK8859VQ orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AK8859VQ order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AK8859VQ?
For technical support, including AK8859VQ datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AK8859VQ requirements.
6.How does Aetrix verify that AK8859VQ is sourced from the original manufacturer or authorized distributors?
All AK8859VQ products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AK8859VQ meets industry standards.
7.What is the process for return or replacement of AK8859VQ?
All AK8859VQ units undergo pre-shipment inspection (PSI). If there is an issue with AK8859VQ, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AK8859VQ part is unused and in its original packaging.
Return procedure for AK8859VQ:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AK8859VQ Tags

-
MCP2120T-I/SL
Microchip Technology

-
LICAL-ENC-MS001
TE Connectivity Linx

-
TW9990AT-NA1-GR
Renesas

-
TVP5151IPBSR
Texas Instruments

-
TVP5150AM1IPBSR
Texas Instruments

-
LICAL-DEC-MS001-T
TE Connectivity Linx

-
ADV7391BCPZ
Analog Devices Inc.

-
ADV7393BCPZ-REEL
Analog Devices Inc.

-
ADV7393BCPZ
Analog Devices Inc.

-
ADV7391WBCPZ
Analog Devices Inc.

-
ADV7181DBCPZ
Analog Devices Inc.

-
ADV7181CBSTZ-REEL
Analog Devices Inc.
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
