Allegro MicroSystems ALT80600KESJSR
- Part No.:
- ALT80600KESJSR
- Manufacturer:
- Allegro MicroSystems
- Category:
- LED Drivers
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
ALT80600KESJSR.pdf
- Description:
- IC LED DRV RGLTR PWM 120MA 24QFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
ALT80600KESJSR from Allegro MicroSystems is an AEC-Q100 qualified multi-output LED driver IC for automotive LCD backlighting, integrating a current-mode boost converter with internal 250 mΩ NMOS switch and four precision current sinks. It delivers up to 120 mA per string across 4 parallel channels, supports 4.5–40 V input, and achieves 15,000:1 PWM dimming contrast ratio at 200 Hz in automotive infotainment displays.
For engineers reviewing the ALT80600KESJSR datasheet, ALT80600KESJSR pinout, ALT80600KESJSR application, or ALT80600KESJSR equivalent, this page provides verified technical context on Pre-Emptive Boost control, 24-pin wettable-flank QFN package mapping, LED string protection logic, and validated alternatives for automotive cluster and center-stack backlight systems.
Technical Context
The ALT80600KESJSR implements a patented Pre-Emptive Boost (PEB) algorithm that dynamically adjusts boost duty cycle before each PWM dimming pulse to maintain stable output voltage and minimize ceramic capacitor audible noise. Its internal error amplifier (1000 µA/V gain) regulates LED current via ISET-set reference and compensates loop through COMP pin with external RZ-CZ network.
It operates in either boost or SEPIC topology, supports programmable switching frequency from 1–2.3 MHz (via FSET resistor or external sync), and includes dithering (1–3 kHz modulation) to reduce EMI. Fault protection covers open/shorted LED strings, overvoltage (55 V SW latch), overtemperature (170 °C shutdown), and input overcurrent via VSENSE-based sensing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 4.5–40 V startup; sustains operation down to 3.9 V - enables robustness during automotive cold-crank and load-dump transients. |
| LED Output Capability | 4 × 120 mA current sinks; up to 44 white LEDs (11 per string, VF ≤ 3.3 V) - supports high-brightness small-size LCD backlighting. |
| PWM Dimming Ratio | 15,000:1 at 200 Hz (PWM only); 150,000:1 (PWM + analog APWM) - meets stringent contrast requirements for automotive displays. |
| Switching Frequency | Programmable 1–2.3 MHz (ALT80600KESJSR); sync-capable with external clock - allows AM-band avoidance and EMI reduction via dithering. |
| Thermal Resistance | RθJA = 37 °C/W (4-layer JEDEC PCB) - requires exposed thermal pad soldered with ≥8 vias for automotive-grade thermal management. |
| Protection Features | OVP (55 V SW latch), UVP, LED short/open detect, cycle-by-cycle overcurrent, thermal shutdown (170 °C) - ensures fail-safe operation in harsh environments. |
| AEC-Q100 Grade | Qualified to Grade 1 (–40 °C to +125 °C ambient) - certified for under-hood and dashboard automotive applications. |
Pinout & Package
ALT80600KESJSR is housed in a 24-pin 4 mm × 4 mm QFN package with wettable flank plating and exposed thermal pad (PAD), requiring direct connection to PCB ground plane via ≥8 thermal vias for thermal integrity and solder inspection.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1–4, 11–14 | LED1–LED4 | Current-sink outputs for LED string cathodes; unused pins must be terminated to AGND via 6.19 kΩ resistor. |
| 5, 21 | AGND / PGND | Separate analog (AGND) and power (PGND) grounds - critical for noise isolation between current-sense and switching paths. |
| 6 | ISET | Sets full-scale LED current (e.g., 120 µA → 120 mA per channel); accuracy ±0.7% typical. |
| 8, 10 | PWM / APWM | Digital PWM dimming input (min 0.3 µs on-time); APWM enables 40–1000 kHz analog dimming for extended contrast ratio. |
| 9, 12 | EN / FAULT | Enable input with 32k-cycle shutdown delay; open-drain FAULT output pulls low on OVP, thermal, or LED fault. |
| 17, 18–19 | OVP / SW | OVP sets output overvoltage threshold (2.5 V ref); SW is internal NMOS drain - connects to boost inductor/diode node. |
| 20 | GATE | Drives external P-MOSFET for input disconnect during overcurrent faults - enhances system-level safety. |
| 22–24 | VIN / VSENSE / CLKOUT | VIN powers IC and serves as current-sense reference; VSENSE monitors VIN–VSENSE = 100 mV trip point; CLKOUT mirrors fSW for multi-converter sync. |
Key Features
| Feature | Design Value |
|---|---|
| Pre-Emptive Boost (PEB) Control | Adjusts boost duty cycle preemptively before each PWM edge to eliminate output ripple and prevent MLCC audible noise - enables stable dimming at ultra-low duty cycles. |
| Programmable Switching Frequency | 1–2.3 MHz range set by FSET resistor or external sync signal - allows EMI optimization and AM-band avoidance without layout changes. |
| Dithering Modulation | Configurable dithering frequency (1–3 kHz) and range (±5% fSW) via DITH capacitor/resistor - reduces peak EMI by spreading spectral energy. |
| Integrated Protection Suite | Detects and latches on LED open/short, boost diode failure, OVP (55 V), UVP, thermal (170 °C), and input overcurrent - eliminates need for discrete fault monitoring. |
| Automotive-Grade Robustness | AEC-Q100 Grade 1 qualification, 4.5–40 V input with 3.9 V hold-up, and wettable-flank QFN package - ensures reliability in stop/start, cold-crank, and vibration-prone environments. |
Applications
| Automotive Infotainment Backlighting | Automotive Digital Cluster Display |
|---|---|
Use Scenario: High-contrast LCD backlight for center-console multimedia units operating across –40 °C to +125 °C ambient. IC Role / Device Role / Timing Role: Four-channel LED driver with Pre-Emptive Boost control regulating 120 mA per string while synchronizing to system clock via CLKOUT. Use Value: 15,000:1 dimming ratio at 200 Hz ensures readable display under direct sunlight and nighttime conditions without visible flicker or ripple-induced noise. |
Use Scenario: Compact TFT-LCD backlight in instrument clusters where space, thermal density, and EMI compliance are critical. IC Role / Device Role / Timing Role: Integrated boost + current sinks replace discrete DC/DC + linear drivers; dithering reduces conducted emissions to meet CISPR 25 Class 5. Use Value: Wettable-flank QFN enables automated optical inspection; 37 °C/W RθJA supports conduction-cooled mounting without heatsinks. |
| Automotive Center Stack Lighting | Automotive Exterior Lighting Control |
Use Scenario: Multi-zone backlight for capacitive-touch center stack with dynamic brightness adjustment based on ambient light sensor input. IC Role / Device Role / Timing Role: Dual-dimming interface (PWM + APWM) allows seamless transition between digital and analog control for smooth intensity ramping. Use Value: 150,000:1 combined dimming ratio eliminates visible steps during gradual dimming - essential for premium UX in luxury vehicle interfaces. |
Use Scenario: Low-power LED array driver for daytime running lights (DRL) or position lamps requiring fault-tolerant operation. IC Role / Device Role / Timing Role: LED string partial-short detection and automatic channel disable prevent single-point failure from propagating to full system outage. Use Value: Open/short LED pin detection during startup avoids uncontrolled current surge; latched OVP prevents damage during load dump events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-string LED driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AL8863T-7DT | Single-channel 1.5 A buck-boost LED driver; no integrated current sinks; requires external MOSFETs and sense resistors. | Targeted at lower-channel-count, higher-current exterior lighting - lacks 4-channel precision sink architecture and PEB control. | Choose AL8863T-7DT only when designing non-backlight systems requiring >1 A per string and flexible topology selection. |
| MAX20050ATP/VY+ | 3-channel AEC-Q100 LED driver with 100 mA/channel; fixed 2.2 MHz fSW; no dithering or PEB; smaller 20-pin TQFN. | Optimized for cost-sensitive cluster modules with ≤3 strings; lacks SEPIC mode and analog+PWM dimming synergy. | Choose MAX20050ATP/VY+ when footprint and BOM count are prioritized over ultra-high dimming ratio and EMI flexibility. |
Compared with AL8863T-7DT and MAX20050ATP/VY+, the ALT80600KESJSR uniquely integrates four matched current sinks, Pre-Emptive Boost, and programmable dithering - making it the only solution qualified for AEC-Q100 Grade 1 automotive LCD backlighting demanding >15,000:1 contrast and <0.3 µs PWM on-time capability.
Availability
ALT80600KESJSR is available at Aetrix Electronics and suitable for automotive infotainment backlighting, digital instrument clusters, and center stack lighting requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for ALT80600KESJSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer of high-performance power ICs and magnetic sensors, specializing in automotive-grade motion control and power management solutions since 1989.
The ALT80600KESJSR belongs to Allegro's automotive LED driver product line, engineered specifically for ultra-high-contrast, low-noise LCD backlighting in infotainment and instrumentation systems subject to harsh electrical and thermal environments.
FAQ
What is the minimum PWM on-time supported by the ALT80600KESJSR?
The ALT80600KESJSR supports a minimum PWM on-time of 0.3 µs, enabled by its Pre-Emptive Boost architecture and fast internal timing control. This specification is guaranteed across the full –40 °C to +125 °C operating range and allows the ALT80600KESJSR to achieve 15,000:1 contrast ratio at 200 Hz without visible flicker or output instability.
Does the ALT80600KESJSR support SEPIC topology in addition to boost mode?
Yes, the ALT80600KESJSR supports both boost and SEPIC configurations, as confirmed in the functional block diagram and typical application schematics. SEPIC mode enables flexible input-to-output voltage ratios - for example, stepping up from 4.5 V or stepping down from 35 V while maintaining regulation - making the ALT80600KESJSR suitable for wide-input automotive systems with variable battery conditions.
How does the ALT80600KESJSR handle LED string faults during startup?
The ALT80600KESJSR performs LED detection during startup by measuring voltage thresholds on each LEDx pin: <120 mV indicates a short-to-ground fault (halts soft-start), ~230 mV identifies an unused channel (disables that sink), and >340 mV confirms active use. Unused pins must be terminated to AGND with 6.19 kΩ resistors to ensure reliable detection - a behavior explicitly defined for the ALT80600KESJSR in the datasheet's LED Detection Phase section.
What thermal design guidance applies to the ALT80600KESJSR's exposed pad?
The ALT80600KESJSR's exposed thermal pad must be soldered directly to the PCB ground plane using at least eight thermal vias to achieve the specified RθJA of 37 °C/W. This configuration ensures proper heat dissipation under maximum load (4 × 120 mA) and maintains junction temperature below 150 °C in automotive ambient conditions - a requirement validated in Allegro's JEDEC 4-layer board thermal characterization for the ALT80600KESJSR.
Can the ALT80600KESJSR synchronize to an external clock, and what is the valid frequency range?
Yes, the ALT80600KESJSR accepts external synchronization via the FSET/SYNC pin across 1–2.3 MHz, matching its internal oscillator range. When synchronized, dithering is disabled, and CLKOUT remains active as long as EN = H - enabling deterministic timing alignment with other converters in multi-rail automotive systems. This capability is explicitly documented for the ALT80600KESJSR in the Electrical Characteristics and Functional Description sections.
ALT80600KESJSR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- DC DC Regulator
- Topology:
- Step-Up (Boost)
- Internal Switch(s):
- Yes
- Number of Outputs:
- 4
- Voltage - Supply (Min):
- 4.5V
- Voltage - Supply (Max):
- 40V
- Voltage - Output:
- 40V
- Current - Output / Channel:
- 120mA
- Frequency:
- 200kHz ~ 2.35MHz
- Dimming:
- Analog, PWM
- Applications:
- Backlight, Lighting
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-QFN (4x4)
ALT80600KESJSR FAQ
1.How can I place an order for ALT80600KESJSR through Aetrix?
Please submit a Request for Quotation (RFQ) for ALT80600KESJSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for ALT80600KESJSR reliable?
The price and inventory of ALT80600KESJSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for ALT80600KESJSR is usually 5 days.
3.What payment methods are accepted for ALT80600KESJSR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for ALT80600KESJSR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for ALT80600KESJSR?
ALT80600KESJSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your ALT80600KESJSR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for ALT80600KESJSR?
For technical support, including ALT80600KESJSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your ALT80600KESJSR requirements.
6.How does Aetrix verify that ALT80600KESJSR is sourced from the original manufacturer or authorized distributors?
All ALT80600KESJSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that ALT80600KESJSR meets industry standards.
7.What is the process for return or replacement of ALT80600KESJSR?
All ALT80600KESJSR units undergo pre-shipment inspection (PSI). If there is an issue with ALT80600KESJSR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The ALT80600KESJSR part is unused and in its original packaging.
Return procedure for ALT80600KESJSR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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