Texas Instruments AM1806EZWT3
- Part No.:
- AM1806EZWT3
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 361-LFBGA
- Datasheet:
-
AM1806EZWT3.pdf
- Description:
- IC MPU SITARA 375MHZ 361NFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AM1806EZWT3 from Texas Instruments is a 375-MHz or 456-MHz ARM926EJ-S™ RISC microprocessor with integrated DDR2/mDDR memory controller, USB 2.0 OTG with PHY, three UARTs, two McBSps, one McASP, LCD controller, VPIF, uPP, and dual PRU cores. It delivers full-featured embedded processing for industrial HMI, medical devices, and building automation systems requiring real-time I/O control and OS support.
For engineers reviewing the AM1806EZWT3 datasheet, AM1806EZWT3 pinout, AM1806EZWT3 application, or AM1806EZWT3 equivalent, this page provides verified technical context, validated package mapping (361-ball NFBGA, 16 mm × 16 mm, 0.80-mm pitch), confirmed peripheral register layout, and two field-tested alternative microprocessors for migration paths in cost- or performance-constrained designs.
Technical Context
The AM1806EZWT3 implements an ARM926EJ-S core with 16-KB instruction and 16-KB data caches, MMU, ETM/ETB trace support, and CP15 coprocessor for memory management. Its subsystem includes dedicated AHB interfaces for peripherals, configurable power domains via PSC, and clock gating across EDMA3, USB, and PRUSS.
It integrates dual-channel EDMA3 with 64 independent DMA channels and 16 QDMA channels, plus two eHRPWM modules (6 outputs total) and three eCAP modules supporting capture or APWM modes. The external memory interface supports 16-bit DDR2 up to 156 MHz and 16-bit mDDR up to 150 MHz, alongside EMIFA for NOR/NAND/SDRAM.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM926EJ-S 32-bit RISC, supports ARMv5TEJ, THUMB, Java acceleration, and MMU-based virtual memory management. |
| Operating Frequency | 375 MHz at 1.2 V or 456 MHz at 1.3 V - defines maximum deterministic throughput for Linux/RTOS execution. |
| On-Chip Memory | 168 KB RAM (including 128 KB SRAM), 64 KB ROM, 16 KB I-Cache, 16 KB D-Cache - enables fast boot and cache-coherent code/data execution. |
| Memory Interfaces | DDR2/mDDR controller (16-bit, up to 156 MHz), EMIFA (8/16-bit async, SDRAM, NAND, NOR) - supports mixed legacy and high-speed memory architectures. |
| Serial Peripherals | 3× UART (16-byte FIFO, RTS/CTS), 2× McASP (16 serializers, TDM/I2S/DIT), 2× McBSP, 2× SPI, 2× I²C - enables multi-protocol audio, telecom, and sensor interfacing. |
| USB & Parallel I/O | USB 2.0 OTG with integrated PHY (host/client), uPP (8–16-bit dual-channel, SDR/DDR, START/ENABLE/WAIT) - connects to FPGAs, ADCs, and legacy parallel peripherals without glue logic. |
| Real-Time Subsystem | PRUSS with two 32-bit RISC cores (4 KB IRAM + 512 B DRAM each), eHRPWM (6 outputs), eCAP (3 modules) - offloads deterministic timing-critical tasks from ARM core. |
Pinout & Package
AM1806EZWT3 uses a 361-ball NFBGA package (ZWT suffix), 16.00 mm × 16.00 mm body size, 0.80-mm ball pitch, RoHS-compliant Pb-free construction. Pin assignments follow TI's standardized ball grid layout with multiplexed functions per bank; unused pins require specific termination per Section 3.8 of SPRS658F.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VP_CLKOUT2 / MM[TRUNCATED_FOR_EXCEL] | Programmable clock output / PRU1 register export | Delivers configurable system clock signal; PRU1_R30[0] and PRU1_R31[1] enable real-time I/O synchronization from PRU subsystem. |
| DVDD3318_C | Core I/O supply (1.8 V / 3.3 V) | Power domain for LVCMOS I/O banks - must be decoupled per TI layout guidelines to ensure signal integrity across 16-bit uPP and McASP interfaces. |
| VSS | Ground reference | System ground plane connection - multiple VSS balls required for low-impedance return paths supporting high-speed DDR2 and USB 2.0 signaling. |
| NC | No-connect terminal | Unbonded pad; must remain unconnected and floating per TI mechanical specification - not usable as spare GPIO or test point. |
Key Features
| Feature | Design Value |
|---|---|
| PRU Subsystem (PRUSS) | Two independent 32-bit RISC cores with dedicated 4 KB IRAM and 512 B DRAM each - enables deterministic real-time control loops without ARM interrupt latency. |
| EDMA3 Controller | Dual-channel architecture with 64 independent DMA channels and 16 QDMA channels - eliminates CPU overhead for high-bandwidth data movement between DDR2, peripherals, and L3 interconnect. |
| Video Port Interface (VPIF) | Supports dual 8-bit BT.656 video capture/display or single 16-bit raw video (8/10/12-bit) - enables direct connection to standard video encoders/decoders without external frame buffers. |
| Universal Parallel Port (uPP) | Configurable 8–16-bit dual-channel interface with START/ENABLE/WAIT handshaking - interoperates with FPGA-based vision processors and high-speed ADCs/DACs. |
| USB 2.0 OTG with PHY | Integrated transceiver supporting host, device, and OTG roles at high/full/low speed - reduces BOM count and PCB area versus discrete PHY solutions. |
Applications
| Industrial HMI | Medical Data Concentrator |
|---|---|
Use Scenario: Touch-enabled panel PC in factory floor environment with local data logging and remote diagnostics over Ethernet/USB. IC Role / Device Role / Timing Role: Primary applications processor running Linux with Qt-based GUI, managing LCD display, touch controller, serial sensors, and USB-connected diagnostic tools. Use Value: Integrated LCD controller, uPP for FPGA-accelerated image processing, and PRUSS for deterministic response to emergency stop inputs reduce system latency and component count. |
Use Scenario: Portable patient monitor aggregating ECG, SpO₂, and temperature data from multiple analog front-ends and transmitting via Wi-Fi or cellular modem. IC Role / Device Role / Timing Role: Central data acquisition engine handling time-synchronized sampling, waveform rendering, and secure data packaging before transmission. Use Value: McASP with DIT capability supports digital audio output to clinical speakers; eHRPWM/eCAP provide precise timing for LED pulse oximetry drive and analog trigger generation. |
| Building Automation Gateway | Set-Top Box Media Processor |
Use Scenario: IP-connected HVAC controller integrating BACnet MS/TP, Modbus RTU, and KNX interfaces while hosting web-based configuration UI. IC Role / Device Role / Timing Role: Protocol translation hub executing multiple concurrent stacks, buffering fieldbus traffic, and serving HTML pages via lightweight web server. Use Value: Dual McBSps and two I²C ports allow simultaneous legacy bus interfacing; DDR2 controller ensures sufficient bandwidth for concurrent network stack and UI rendering. |
Use Scenario: Cost-optimized HD media player decoding MPEG-4/AVC streams, driving HDMI output, and supporting USB storage playback. IC Role / Device Role / Timing Role: Baseband processor handling video decode acceleration (via software libraries), audio post-processing, and HDMI timing generation through LCD controller registers. Use Value: VPIF enables direct BT.656 video capture for secondary camera input; USB 2.0 OTG supports mass storage class for external HDD playback without additional bridge ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ARM9-based applications processors.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM1808ZWT | Same ZWT package, identical pinout, but rated for 456 MHz at 1.3 V only; includes enhanced security features (AES, SHA, RNG) and additional 64 KB on-chip RAM. | Required for designs needing cryptographic acceleration or higher sustained throughput under thermal constraints. | Select AM1808ZWT when cryptographic services or >375 MHz deterministic performance are mandatory; verify voltage rail stability for 1.3-V operation. |
| AM3352BZCZ100 | ARM Cortex-A8 core (1 GHz), PRU-ICSS instead of PRUSS, single DDR2 channel, no VPIF or uPP; 324-ball ZCZ package (15 mm × 15 mm). | Suitable for next-generation designs prioritizing higher CPU throughput and modern PRU firmware toolchain over legacy video/parallel interfaces. | Choose AM3352BZCZ100 for migration paths targeting Cortex-A8 ecosystem, TI SDK 6.x, and reduced BOM cost where VPIF/uPP are not needed. |
Compared with AM1806EZWT3, AM1808ZWT offers higher clock headroom and hardware crypto, while AM3352BZCZ100 shifts to Cortex-A8 with updated PRU tooling but drops VPIF and uPP - making AM1806EZWT3 optimal for legacy video, parallel I/O, and deterministic PRU-based control within its 375/456 MHz envelope.
Availability
AM1806EZWT3 is available at Aetrix Electronics and suitable for industrial HMI, medical data concentrators, and building automation gateways requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for Class II medical and UL-certified equipment.
Supply support for AM1806EZWT3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of experience in industrial, automotive, and medical silicon design.
The AM1806EZWT3 belongs to TI's Sitara™ ARM processor family, designed specifically for cost-sensitive, real-time embedded applications requiring rich peripheral integration, OS support, and deterministic I/O control without external co-processors.
FAQ
What is the maximum DDR2 memory speed supported by the AM1806EZWT3?
The AM1806EZWT3 DDR2/mDDR memory controller supports up to 156 MHz for DDR2 and 150 MHz for mobile DDR. This translates to 312 MT/s effective data rate for 16-bit DDR2 interfaces. These speeds are validated under recommended operating conditions in SPRS658F Section 6.11 and require proper PCB layout with matched trace lengths and controlled impedance for reliable operation at rated frequency.
Does the AM1806EZWT3 include an integrated USB PHY?
Yes, the AM1806EZWT3 integrates a full-speed and high-speed USB 2.0 OTG PHY compliant with the USB 2.0 specification. The PHY supports host, device, and OTG roles and requires only external 0.22-μF filtering on USB0_VDDA12 per Section 3.7.17 of SPRS658F - eliminating the need for a discrete PHY IC and reducing bill-of-materials cost.
How many independent PRU cores does the AM1806EZWT3 contain?
The AM1806EZWT3 contains two independent programmable real-time unit (PRU) cores within the PRUSS subsystem. Each core has 4 KB of instruction RAM and 512 bytes of data RAM, and both can be disabled via software to save power. Register R30 of each PRU is exported externally, enabling synchronized I/O control with sub-microsecond latency.
What peripheral interfaces does the AM1806EZWT3 provide for audio applications?
The AM1806EZWT3 provides one Multichannel Audio Serial Port (McASP) with 16 serializers, transmit/receive clocks, FIFO buffers, and support for TDM, I²S, and DIT formats. It also includes two Multichannel Buffered Serial Ports (McBSPs) with FIFOs and AC97 codec interface capability - enabling simultaneous connection to multiple audio codecs, DSPs, or digital microphones in voice-enabled edge devices.
Is the AM1806EZWT3 pin-compatible with other members of the AM18xx family?
Yes, the AM1806EZWT3 shares identical pinout and package dimensions (361-ball ZWT) with AM1808ZWT and AM1810ZWT. This allows direct PCB reuse across performance tiers - for example, upgrading from 375 MHz (AM1806) to 456 MHz (AM1808) without layout changes, provided power delivery and thermal design accommodate the higher voltage and dissipation.
AM1806EZWT3 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 361-LFBGA
- Series:
- Sitara™
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM926EJ-S
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 375MHz
- Co-Processors/DSP:
- System Control; CP15
- RAM Controllers:
- LPDDR, DDR2
- Graphics Acceleration:
- No
- Display & Interface Controllers:
- LCD
- Ethernet:
- -
- SATA:
- -
- USB:
- USB 2.0 + PHY (1)
- Voltage - I/O:
- 1.8V, 3.3V
- Operating Temperature:
- 0°C ~ 90°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 361-NFBGA (16x16)
- Additional Interfaces:
- I2C, McASP, McBSP, SPI, MMC/SD, UART
AM1806EZWT3 FAQ
1.How can I place an order for AM1806EZWT3 through Aetrix?
Please submit a Request for Quotation (RFQ) for AM1806EZWT3 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AM1806EZWT3 reliable?
The price and inventory of AM1806EZWT3 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AM1806EZWT3 is usually 5 days.
3.What payment methods are accepted for AM1806EZWT3?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AM1806EZWT3 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AM1806EZWT3?
AM1806EZWT3 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AM1806EZWT3 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AM1806EZWT3?
For technical support, including AM1806EZWT3 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AM1806EZWT3 requirements.
6.How does Aetrix verify that AM1806EZWT3 is sourced from the original manufacturer or authorized distributors?
All AM1806EZWT3 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AM1806EZWT3 meets industry standards.
7.What is the process for return or replacement of AM1806EZWT3?
All AM1806EZWT3 units undergo pre-shipment inspection (PSI). If there is an issue with AM1806EZWT3, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AM1806EZWT3 part is unused and in its original packaging.
Return procedure for AM1806EZWT3:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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