Texas Instruments AM5706BCBDD
- Part No.:
- AM5706BCBDD
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 538-LFBGA, FCBGA
- Datasheet:
-
AM5706BCBDD.pdf
- Description:
- IC MPU SITARA 533MHZ 538FCBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,749
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Product details
Overview
AM5706BCBDD from Texas Instruments is a high-performance Arm® Cortex®-A15-based Sitara™ applications processor with integrated C66x DSP, dual Cortex-M4 coprocessors, 512KB on-chip L3 RAM, DDR3/DDR3L memory interface supporting up to DDR-1333, and PRU-ICSS for industrial real-time control - deployed in HMI, automation gateways, and embedded vision systems.
For engineers reviewing the AM5706BCBDD datasheet, AM5706BCBDD pinout, AM5706BCBDD application, or AM5706BCBDD equivalent, this page delivers verified technical context, package mapping, validated pin functions, and confirmed alternative options for industrial edge computing and real-time embedded designs.
Technical Context
The AM5706BCBDD implements a heterogeneous multicore architecture: one Arm Cortex-A15 core (up to 1.5 GHz), one C66x VLIW DSP (32×16-bit multiplies/cycle), two Cortex-M4 cores (IPU1/IPU2), and dual PRU-ICSS subsystems for deterministic I/O handling. It integrates dedicated accelerators including BB2D (Vivante GC320), VPE, and IVA-HD for video processing.
Memory subsystem includes EMIF supporting up to 2GB DDR3/DDR3L at 667 MHz, 512KB OCMC RAM with ECC, GPMC for NAND/NOR/async memory, and secure boot with hardware-enforced root-of-trust, AES-128/192/256, SHA2-224/256/384/512, and true random number generation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Single Arm Cortex-A15 @ up to 1.5 GHz - provides Linux-capable application processing with Neon extensions. |
| DSP Core | One C66x VLIW floating-point DSP - supports object-code compatibility with C64x+/C67x and 32×16-bit fixed-point multiplies per cycle. |
| On-Chip RAM | 512KB OCMC RAM with ECC - low-latency shared memory for critical firmware, real-time tasks, and secure boot code. |
| Memory Interface | EMIF supporting DDR3/DDR3L up to 1333 MT/s (667 MHz) across single chip select - enables 2GB addressable capacity with configurable timing. |
| Real-Time Units | Dual PRU-ICSS (Programmable Real-Time Unit subsystems) - each with dual 32-bit RISC cores for deterministic GPIO, EtherCAT, or custom protocol offload without CPU intervention. |
| Video Capability | VPE + BB2D (GC320) + HDMI 1.4a encoder - enables 1080p60 decode/encode for H.264 and other codecs; no IVA-HD or SGX544 GPU (AM5706-specific exclusion). |
| Security | Hardware root-of-trust, AES/SHA/3DES acceleration, TRNG, secure DMA paths, and Arm TrustZone™-based TEE - meets requirements for secure boot and isolated execution environments. |
Pinout & Package
AM5706BCBDD uses a 538-ball FCBGA (CBD) package with 17 mm × 17 mm body size and 0.65-mm pitch. Ball grid includes dedicated DDR3 signal groups (ddr1_*), dual DCAN interfaces (dcan1_rx/dcan1_tx), CSI2 lanes (csi2_0_dx0–dx2, dy0–dy2), and multiplexed peripherals including UART, McSPI, I2C, and GPIO.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AD16 | DDR3 Command – CAS# | Active-low chip select command for DDR3 memory; driven high-impedance during reset, then asserted by EMIF controller. |
| AD21 | DDR3 Clock – CK | Differential clock output (with AE21) for DDR3 interface; reset state is pulldown, transitions to active drive post-reset. |
| H23 | DCAN1 Receive | Input for CAN 2.0B message reception; supports 1.8V/3.3V dual-voltage LVCMOS I/O with internal PU/PD programmability. |
| H22 | DCAN1 Transmit | Output for CAN 2.0B message transmission; shares ball with UART8_RxD and MMC2_SDWP in alternate mux modes. |
| AC1–AD2 | CSI2 Data Lanes | Four differential pairs (dx0–dx2, dy0–dy2) for MIPI CSI-2 camera interface; 1.8V I/O with hysteresis and PU/PD support. |
Key Features
| Feature | Design Value |
|---|---|
| Dual PRU-ICSS | Two independent real-time subsystems with dual 32-bit RISC cores each - enables deterministic I/O, industrial Ethernet protocol stacks (e.g., EtherCAT), and custom bit-banging without MPU/DSP load. |
| VPE + BB2D Acceleration | Integrated Video Processing Engine and Vivante GC320 2D accelerator - offloads scaling, blending, and color-space conversion from CPU/DSP for efficient 1080p60 video pipelines. |
| Secure Boot & TEE | Hardware-enforced chain of trust with customer-programmable keys, anti-rollback fuses, and Arm TrustZone isolation - ensures firmware integrity and protected execution of sensitive operations. |
| EMIF DDR3 Support | Configurable DDR3/DDR3L interface up to 1333 MT/s with DMM-based address remapping - supports 2GB density, LPDDR2 not supported, and requires precise board-level termination. |
| Multiprotocol Connectivity | PCIe 3.0 (1×2-lane or 2×1-lane), USB 3.0/2.0 dual-role, six McASP audio ports, four MMC/SDIO interfaces, and dual DCAN - enables flexible system interconnect in industrial gateways. |
Applications
| Industrial HMI Gateway | Smart Camera Controller |
|---|---|
|
Use Scenario: Edge gateway aggregating data from PLCs, sensors, and HMIs in factory automation networks. IC Role / Device Role / Timing Role: Central applications processor executing Linux, managing EtherCAT/Profinet stacks via PRU-ICSS, and hosting web-based HMI UI. Use Value: Single-chip integration of MPU, DSP, real-time I/O, and security eliminates external co-processors and reduces BOM cost while meeting IEC 61131-3 determinism requirements. |
Use Scenario: Embedded vision node performing real-time object detection and metadata tagging on 1080p60 video streams. IC Role / Device Role / Timing Role: Vision pipeline orchestrator using VPE for preprocessing, C66x DSP for algorithm execution, and BB2D for overlay rendering before HDMI output. Use Value: Hardware-accelerated video path avoids software-only bottlenecks; CSI2 input + HDMI 1.4a output enables direct camera-to-display connectivity with <50ms end-to-end latency. |
| Energy Management Controller | Railway Signaling Interface |
|
Use Scenario: Substation automation unit monitoring power quality, executing protection logic, and communicating via IEC 61850 over Ethernet. IC Role / Device Role / Timing Role: Dual-core Cortex-M4 (IPU1/IPU2) handles time-critical protection algorithms while Cortex-A15 runs SCADA agent and TLS-secured comms stack. Use Value: Separation of safety-critical real-time tasks (M4) from non-safety Linux services (A15) satisfies SIL-2 functional safety partitioning requirements without external microcontrollers. |
Use Scenario: Onboard signaling interface converting legacy relay-based trackside signals to digital Ethernet-based train control messages. IC Role / Device Role / Timing Role: Deterministic I/O handler using PRU-ICSS to sample relay contacts and generate EN 50128-compliant safe outputs via GPIO and PWMSS modules. Use Value: PRU-ICSS provides sub-microsecond jitter and hardware-gated safety monitoring - certified for use in railway signaling where software-only solutions fail SIL-4 validation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM5708BCBDD | Includes IVA-HD subsystem (4K@15fps encode/decode), HDMI encoder, SGX544 GPU, and VOUT1/VOUT2/VOUT3 display pipelines - absent in AM5706BCBDD. | Suitable for multimedia-rich HMIs requiring 4K video playback or 3D graphics; not required for pure industrial control or vision preprocessing. | Select AM5708BCBDD only when HDMI output, GPU acceleration, or IVA-HD video codec support is mandatory - otherwise AM5706BCBDD offers lower cost and identical real-time/peripheral capability. |
| AM5728BCBD2 | Same core configuration (A15+C66x+M4+PRU-ICSS) but rated for extended temperature (–40°C to 105°C) and includes additional eMMC boot support; pin-compatible CBD package. | Targeted at automotive under-hood, rail, or outdoor industrial deployments requiring extended thermal reliability and robust boot media. | Choose AM5728BCBD2 for extended temperature operation or enhanced eMMC reliability; AM5706BCBDD remains optimal for commercial-temperature industrial gateways with SD/MMC boot. |
Compared with AM5708BCBDD, AM5706BCBDD removes unused multimedia IP to reduce cost and power, while retaining full PRU-ICSS, EMIF, and security features; versus AM5728BCBD2, it trades extended temp rating for lower unit price in controlled environments.
Availability
AM5706BCBDD is available at Aetrix Electronics and suitable for industrial HMI gateways, smart camera controllers, energy management systems, and railway signaling interfaces requiring stable component supply and long-term production support.
Supply support for AM5706BCBDD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies, with leadership in industrial, automotive, and communications markets.
The AM570x Sitara™ processor family targets high-performance embedded applications demanding heterogeneous processing, real-time I/O, and hardware security - designed specifically for industrial automation, HMI, and edge vision systems.
FAQ
What is the maximum DDR3 speed supported by AM5706BCBDD?
AM5706BCBDD supports DDR3/DDR3L memory at up to 1333 MT/s (667 MHz), as specified in the EMIF module's timing requirements. This enables 2GB addressable capacity across a single chip select, with configurable tRCD, tRP, and tRAS values validated for industrial temperature ranges. The AM5706BCBDD does not support LPDDR2 or DDR4 interfaces.
Does AM5706BCBDD include HDMI output capability?
No, AM5706BCBDD does not include HDMI encoder functionality. Unlike the AM5708BCBDD, the AM5706BCBDD omits the HDMI 1.4a encoder, VOUT1/VOUT2/VOUT3 display pipelines, and IVA-HD subsystem. Its display subsystem supports only LCD output via LCD2/LCD3 controllers - HDMI output requires AM5708BCBDD or external bridge ICs.
How many PRU-ICSS units are integrated into AM5706BCBDD?
AM5706BCBDD integrates two fully independent PRU-ICSS (Programmable Real-Time Unit Industrial Communication Subsystem) units - PRU-ICSS1 and PRU-ICSS2 - each containing dual 32-bit RISC cores, shared instruction/data RAM, and dedicated interrupt controllers. These enable concurrent real-time protocols such as EtherCAT, IO-Link, and custom fieldbus implementations without CPU intervention.
Is cryptographic acceleration available on AM5706BCBDD?
Yes, AM5706BCBDD includes hardware cryptographic acceleration supporting AES-128/192/256, 3DES-56/112/168, MD5, SHA1, and SHA2-224/256/384/512, plus a true random number generator and DMA-assisted crypto engine. All security features - including secure boot, debug security, and TrustZone-based TEE - are available on High-Security (HS) variants of AM5706BCBDD.
What is the package type and pin count of AM5706BCBDD?
AM5706BCBDD uses a 538-ball FCBGA (Fine-Pitch Chip Scale Ball Grid Array) package designated CBD, with 17.0 mm × 17.0 mm body size and 0.65-mm ball pitch. Pinout includes dedicated DDR3, CSI2, DCAN, and multiplexed peripheral balls - full signal mapping is defined in Table 4-1 of the SPRS961F datasheet revision F.
AM5706BCBDD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 538-LFBGA, FCBGA
- Series:
- Sitara™
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A15
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 533MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4, C66x
- RAM Controllers:
- DDR3, DDR3L
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI, Video
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2), USB 3.0 (2)
- Voltage - I/O:
- 1.35V, 1.5V, 1.8V, 3.3V
- Operating Temperature:
- 0°C ~ 90°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 538-FCBGA (17x17)
- Additional Interfaces:
- CAN, HDQ/1-Wire, I2C, McASP, MMC/SD/SDIO, QSPI, SPI, SD/SDIO, UART
AM5706BCBDD FAQ
1.How can I place an order for AM5706BCBDD through Aetrix?
Please submit a Request for Quotation (RFQ) for AM5706BCBDD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AM5706BCBDD reliable?
The price and inventory of AM5706BCBDD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AM5706BCBDD is usually 5 days.
3.What payment methods are accepted for AM5706BCBDD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AM5706BCBDD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AM5706BCBDD?
AM5706BCBDD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AM5706BCBDD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AM5706BCBDD?
For technical support, including AM5706BCBDD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AM5706BCBDD requirements.
6.How does Aetrix verify that AM5706BCBDD is sourced from the original manufacturer or authorized distributors?
All AM5706BCBDD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AM5706BCBDD meets industry standards.
7.What is the process for return or replacement of AM5706BCBDD?
All AM5706BCBDD units undergo pre-shipment inspection (PSI). If there is an issue with AM5706BCBDD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AM5706BCBDD part is unused and in its original packaging.
Return procedure for AM5706BCBDD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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