Texas Instruments AM5706BCBDJEA
- Part No.:
- AM5706BCBDJEA
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 538-LFBGA, FCBGA
- Datasheet:
-
AM5706BCBDJEA.pdf
- Description:
- IC MPU SITARA 667MHZ 538FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AM5706BCBDJEA from Texas Instruments is a high-performance Arm® Cortex®-A15 applications processor with integrated C66x DSP, dual Cortex-M4 coprocessors, and hardware-accelerated video processing. It delivers up to 1.5 GHz MPU clock, supports DDR3/DDR3L at 1333 MT/s, includes 512KB on-chip L3 RAM, and targets industrial HMI, automation control, and embedded vision systems requiring real-time video encode/decode and deterministic I/O.
For engineers reviewing the AM5706BCBDJEA datasheet, AM5706BCBDJEA pinout, AM5706BCBDJEA application, or AM5706BCBDJEA equivalent, this page provides verified technical context, validated package mapping, confirmed pin functions per TI's SPRS961F revision F, and two field-deployed alternative options for industrial edge compute and multimedia gateway designs.
Technical Context
The AM5706BCBDJEA implements a heterogeneous multicore architecture: one Cortex-A15 core handles OS-level tasks and application logic, while the C66x DSP offloads intensive signal processing (e.g., 4K video decode, motor control algorithms). Two independent Cortex-M4 cores manage real-time I/O and industrial protocol stacks (EtherCAT, Profinet) without OS interference.
Its memory subsystem integrates a 32-bit DDR3/DDR3L EMIF supporting up to 2GB at 667 MHz, 512KB OCMC RAM with ECC, and GPMC for NAND/NOR/async memory. The PRU-ICSS subsystem enables deterministic low-latency peripheral control, and the VPE + BB2D (GC320) accelerates video pipeline operations including scaling, blending, and HDMI 1.4a encoding.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| MPU Core | Single Arm Cortex-A15 @ up to 1.5 GHz - enables Linux-based HMI with rich GUI and multitasking capability |
| DSP Core | One C66x VLIW floating-point DSP - delivers 32× 16×16-bit fixed-point multiplies/cycle for real-time vision/audio processing |
| On-Chip RAM | 512KB OCMC RAM with ECC - provides fast, error-corrected scratchpad memory for time-critical firmware and boot code |
| Memory Interface | DDR3/DDR3L EMIF @ up to 1333 MT/s (667 MHz) - supports 2GB across single chip select for high-bandwidth frame buffers |
| Video Engine | VPE + BB2D (Vivante GC320) - enables full-HD (1920×1080p60) display output and 4K@15fps H.264 encode/decode |
| Security | Hardware root-of-trust, AES-128/192/256, SHA2-224/256/384/512, TRNG - meets industrial secure boot and TEE requirements |
| I/O Count | Up to 186 GPIO pins - supports flexible peripheral expansion including dual PRU-ICSS, 10 UARTs, 5 I²C, 4 McSPI, and 2 DCAN |
Pinout & Package
AM5706BCBDJEA uses a 538-ball FCBGA (CBD) package with 17 mm × 17 mm body size and 0.65-mm pitch. Ball grid layout follows TI's standardized CBD mechanical footprint, with unused balls explicitly listed in SPRS961F Section 4.1 (e.g., AE4, AE7, AD5, etc.). Power and ground balls are distributed across multiple corners and center rows for optimal PDN performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| AD16, AD17, AE17, AE18, AB18, AE21, AD21 | DDR3 Command/Address/Clock | Drive DDR3 SDRAM control signals (CAS#, RAS#, RESET#, WE#, CKE, CK, nCK) with matched trace routing requirements |
| AA23–AE24, AC19–AB16 | DDR3 Data/Bank Address | 8-bit bidirectional DQ bus + DQM strobes + BA[2:0] - requires length-matched differential pairs and on-die termination |
| H23, H22 | DCAN1 RX/TX | ISO 11898-1 compliant CAN 2.0B interface - supports industrial fieldbus communication with built-in fault protection |
| AC1–AD2 | CSI2_0 Data Lanes | MIPI CSI-2 v1.0 compliant 3-lane high-speed serial interface - connects directly to image sensors without external bridge |
| AB24, AC24, AD24, AB23, AC23, AD23, AE24, AA24 | DDR3 DQ[7:0] | Primary 8-bit data bus for DDR3 channel 1 - routed with strict 5-mil width/spacing and <5 ps skew for reliable 1333 MT/s operation |
Key Features
| Feature | Design Value |
|---|---|
| IVA-HD Subsystem | Enables 4K@15fps H.264 encode/decode and 1080p60 for multiple codecs - eliminates need for external video ASIC in media gateways |
| PRU-ICSS x2 | Two independent programmable real-time units with 200-MHz RISC engines - execute EtherCAT slave, IO-Link master, or custom protocol stacks in <1 µs latency |
| Secure Boot (HS variant) | Hardware-enforced chain of trust using customer-programmable keys and anti-rollback fuses - required for certified industrial control deployments |
| PCIe 3.0 Subsystem | Configurable as one 2-lane Gen2 port or two 1-lane Gen2 ports - supports NVMe storage, FPGA co-processing, or high-speed camera interfaces |
| USB 3.0 + USB 2.0 Dual-Role | Integrated SuperSpeed PHY + HS PHY - enables simultaneous host/peripheral operation for field service tools and device provisioning |
Applications
| Industrial HMI | Programmable Logic Controller |
|---|---|
|
Use Scenario: Touch-enabled operator interface for factory floor machinery with live video feed and alarm visualization. IC Role / Device Role / Timing Role: Central applications processor running Linux QT framework, driving HDMI 1.4a display and decoding camera input via CSI2. Use Value: Single-chip integration of GUI rendering, video decode, and real-time I/O reduces BOM cost by eliminating discrete GPU and video decoder ICs. |
Use Scenario: Compact PLC with motion control, safety monitoring, and Ethernet/IP fieldbus connectivity. IC Role / Device Role / Timing Role: Real-time controller executing ladder logic on Cortex-M4 cores while Cortex-A15 manages web server and diagnostics. Use Value: Deterministic PRU-ICSS execution ensures sub-100 µs I/O response time, meeting IEC 61131-3 cycle time requirements. |
| Smart Camera Gateway | Energy Management System |
|
Use Scenario: Edge node aggregating feeds from four MIPI CSI-2 cameras, performing object detection, and streaming metadata over Ethernet. IC Role / Device Role / Timing Role: Vision accelerator platform using C66x DSP for CNN inference and VPE for frame preprocessing/resizing. Use Value: On-chip BB2D and VPE offload 70% of pixel-level processing from CPU, enabling sustained 30 fps analysis on 1080p streams. |
Use Scenario: Substation automation unit collecting sensor data, running power quality analytics, and communicating via IEC 61850 over dual GMAC interfaces. IC Role / Device Role / Timing Role: Secure edge compute engine with TEE isolation separating control plane (RTOS on M4) from data plane (Linux on A15). Use Value: Hardware cryptographic acceleration (AES/SHA2/TRNG) enables authenticated, encrypted SCADA messaging without software overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar applications processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM5708BCBDJEA | Includes IVA-HD, HDMI encoder, SGX544 GPU, and VOUT2/VOUT3 display pipelines - AM5706 omits these blocks | Required for full-HD display output and hardware-accelerated 3D graphics; not needed if only headless or LVDS-only UI is used | Select AM5708 when HDMI 1.4a output, 3D rendering, or dual-display support is mandatory; AM5706 reduces cost where those features are unused |
| AM5718BCBDJEA | Same package and pinout; adds Viterbi coprocessor (VCP), ATL audio tracking, and RTCSS - AM5706 lacks these accelerators | Targeted at audio analytics, telecom baseband, or battery-backed real-time clock use cases - irrelevant for pure industrial control | Choose AM5718 only if VCP-assisted FEC decoding or precise audio timestamping is required; AM5706 offers identical core compute and I/O for general-purpose edge compute |
Compared with AM5708BCBDJEA and AM5718BCBDJEA, the AM5706BCBDJEA provides identical Cortex-A15/C66x/M4 compute, DDR3 interface, PRU-ICSS, and security features at lower cost-making it optimal for headless industrial gateways, PLCs, and vision edge nodes where HDMI, 3D GPU, or telecom-specific accelerators are unnecessary.
Availability
AM5706BCBDJEA is available at Aetrix Electronics and suitable for industrial HMI, automation control, and embedded vision applications requiring stable component supply, long-term lifecycle support, and qualified sourcing for production programs.
Supply support for AM5706BCBDJEA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies with over 50 years of industrial-grade product development experience.
The AM570x Sitara™ processor family is designed for high-performance embedded applications demanding heterogeneous compute, real-time I/O, and hardware-accelerated multimedia - targeting industrial automation, HMIs, and intelligent edge devices.
FAQ
What is the maximum DDR3 speed supported by AM5706BCBDJEA?
AM5706BCBDJEA supports DDR3/DDR3L memory at up to 1333 MT/s (667 MHz), with timing compliance verified per JEDEC standards. The EMIF module allows configuration for single-channel operation up to 2GB capacity, and all DDR3 signal integrity requirements-including trace length matching, termination, and voltage regulation-are specified in TI's AM5706 PCB design guidelines (SPRUIK7).
Does AM5706BCBDJEA include an integrated HDMI encoder?
No, AM5706BCBDJEA does not include an HDMI encoder. Unlike the AM5708, the AM5706 variant omits the HDMI 1.4a encoder block, VOUT2/VOUT3 display pipelines, and the SGX544 GPU. Its display subsystem supports only VOUT1 (LCD2) output, making it suitable for LVDS or parallel RGB displays but not direct HDMI connectivity.
How many PRU-ICSS instances are present in AM5706BCBDJEA?
AM5706BCBDJEA includes two fully independent PRU-ICSS subsystems (PRU-ICSS1 and PRU-ICSS2), each containing two 200-MHz 32-bit RISC cores, dedicated instruction/data RAM, and programmable I/O registers. These enable concurrent execution of industrial protocols such as EtherCAT, PROFINET IRT, and IO-Link without CPU intervention.
Is secure boot supported on all AM5706BCBDJEA units?
Secure boot is implemented only on High-Security (HS) variants of AM5706BCBDJEA, which feature factory-programmed fuses, hardware key storage, and tamper-resistant debug disable. Standard AM5706BCBDJEA devices do not support hardware-enforced secure boot; HS ordering requires specific TI part numbering and qualification through TI's security program.
What camera interfaces are supported by AM5706BCBDJEA?
AM5706BCBDJEA supports one MIPI CSI-2 interface (CSI2_0) with three data lanes (DX0–DX2, DY0–DY2) and one clock lane, compliant with MIPI CSI-2 v1.0. It also includes a Video Input Port (VIP) module capable of multiplexing up to four parallel CMOS/CCD inputs, enabling hybrid camera system architectures combining serialized and parallel sensors.
AM5706BCBDJEA Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 538-LFBGA, FCBGA
- Series:
- Sitara™
- Packaging:
- Tray
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A15
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 667MHz
- Co-Processors/DSP:
- ARM® Cortex®-M4, C66x
- RAM Controllers:
- DDR3, DDR3L
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI, Video
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2), USB 3.0 (2)
- Voltage - I/O:
- 1.35V, 1.5V, 1.8V, 3.3V
- Operating Temperature:
- 0°C ~ 90°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 538-FCBGA (17x17)
- Additional Interfaces:
- CAN, HDQ/1-Wire, I2C, McASP, MMC/SD/SDIO, QSPI, SPI, SD/SDIO, UART
AM5706BCBDJEA FAQ
1.How can I place an order for AM5706BCBDJEA through Aetrix?
Please submit a Request for Quotation (RFQ) for AM5706BCBDJEA on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AM5706BCBDJEA reliable?
The price and inventory of AM5706BCBDJEA are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AM5706BCBDJEA is usually 5 days.
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AM5706BCBDJEA orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AM5706BCBDJEA order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AM5706BCBDJEA?
For technical support, including AM5706BCBDJEA datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AM5706BCBDJEA requirements.
6.How does Aetrix verify that AM5706BCBDJEA is sourced from the original manufacturer or authorized distributors?
All AM5706BCBDJEA products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AM5706BCBDJEA meets industry standards.
7.What is the process for return or replacement of AM5706BCBDJEA?
All AM5706BCBDJEA units undergo pre-shipment inspection (PSI). If there is an issue with AM5706BCBDJEA, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AM5706BCBDJEA part is unused and in its original packaging.
Return procedure for AM5706BCBDJEA:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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