Texas Instruments AM5718BABCXASR
- Part No.:
- AM5718BABCXASR
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 760-BFBGA, FCBGA
- Datasheet:
-
AM5718BABCXASR.pdf
- Description:
- IC MPU SITARA 1.5GHZ 760FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AM5718BABCXASR from Texas Instruments is a high-performance Sitara™ Arm® applications processor featuring a single-core Cortex®-A15 CPU, dual C66x VLIW DSP cores, dual Cortex®-M4 coprocessors (IPU1/IPU2), IVA-HD video subsystem supporting 4K@15fps H.264 encode/decode, and PowerVR® SGX544 3D GPU. It integrates DDR3/DDR3L EMIF (up to 2GB, 1333 MT/s), PCIe Gen2 (2-lane or dual 1-lane), dual Gigabit Ethernet, and 215 GPIOs in a 760-pin FCBGA package for industrial HMI and automation edge nodes.
For engineers reviewing the AM5718BABCXASR datasheet, AM5718BABCXASR pinout, AM5718BABCXASR application, or AM5718BABCXASR equivalent, key selection considerations include verified 4K video processing capability, dual PRU-ICSS support for real-time industrial protocols, secure boot with customer-programmable keys (Silicon Revision 2.1), cryptographic acceleration (AES-128/192/256, SHA2-224/256/384/512), and thermal/power specifications validated for continuous operation in extended temperature industrial environments.
Technical Context
The AM5718BABCXASR implements a heterogeneous multicore architecture with tightly coupled interconnects: Level 3 (L3) and Level 4 (L4) interconnects route traffic between Arm A15, C66x DSP, M4 coprocessors, IVA-HD, VPE, BB2D, and peripherals. Its memory subsystem includes 512KB on-chip OCMC RAM with ECC, DDR3/DDR3L EMIF supporting up to 1333 MT/s, and GPMC for NAND/NOR/async memory expansion.
Real-time determinism is enabled by two independent PRU-ICSS subsystems, each with dual 32-bit RISC cores, dedicated local memories, and programmable I/O for EtherCAT®, PROFINET, and other industrial Ethernet protocols. Security is enforced via hardware root-of-trust, TrustZone®-based TEE, secure DMA paths, and firewall-protected interconnects - all confirmed for Silicon Revision 2.1.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | Single Arm® Cortex®-A15 @ up to 1.5 GHz - delivers Linux-capable application processing with Neon™ SIMD extensions for media workloads. |
| DSP Core | Dual TI C66x VLIW floating-point DSPs - fully object-code compatible with C64x+/C67x, enabling reuse of legacy signal processing libraries. |
| Video Capability | IVA-HD + VPE supports 4K@15fps H.264 encode/decode and 1080p60 for multiple codecs - enables embedded vision gateways without external video ASICs. |
| Memory Interface | DDR3/DDR3L EMIF supporting up to 2GB across single chip select at 1333 MT/s - provides bandwidth for concurrent OS, UI, and video pipelines. |
| Security Features | Hardware-enforced secure boot, customer-programmable eFuses (SR 2.1), AES/SHA2/3DES crypto acceleration, and TrustZone® TEE - meets industrial security certification requirements. |
| Connectivity | PCIe Gen2 (2-lane or dual 1-lane), dual Gigabit Ethernet switch, SATA Gen2, USB 3.0/2.0 dual-role, 5× I2C, 10× UART, 4× McSPI, 2× DCAN - supports full-stack industrial gateway I/O consolidation. |
| Package | 760-pin FCBGA, 23 mm × 23 mm, 0.8-mm pitch - qualified for industrial temperature range and compatible with standard BGA reflow profiles. |
Pinout & Package
AM5718BABCXASR uses a 23 mm × 23 mm, 0.8-mm pitch, 760-ball FCBGA (FCBGA-N760) package. Ball assignment follows TI's ABC package variant with defined power, ground, signal, and reserved ball locations per SPRS957I Rev I. Unused balls require specific tie-offs: AE15/AC15/AE14/D20/AD17/AC16/V27/AH25/AE27/AD27/Y28 must connect to GND via external pull resistors; E20/D21/E23/C20/C21/V28/F18/AG25/AE28/AD28/Y27/F17/C25 must connect to corresponding power supplies via external pull resistors.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VSS / VDD_CORE / VDD_MPU / VDD_DSP / VDD_GPU / VDD_DDR / VDD_IO | Power supply domains | Separate regulated rails for MPU, DSP, GPU, DDR, and I/O - enable independent voltage scaling and thermal management per subsystem. |
| DDR_DQ[0:63] / DDR_DM[0:7] / DDR_CLK / DDR_CKE / DDR_CS / DDR_RAS / DDR_CAS / DDR_WE | DDR3/DDR3L interface signals | 64-bit data bus with 8-bit ECC support, differential clock, and command/address lines - supports JEDEC-compliant DDR3-1333 operation. |
| PCIe_REFCLK_P/N / PCIe_TX[0:1]_P/N / PCIe_RX[0:1]_P/N | PCIe Gen2 differential lanes | Two configurable 5-Gbps differential pairs - can be configured as one 2-lane port or two independent 1-lane ports per silicon revision 2.0/2.1. |
| GPMC_AD[0:29] / GPMC_A[0:12] / GPMC_OEN / GPMC_WEN / GPMC_CSN | General-Purpose Memory Controller interface | 30-bit address/data multiplexed bus supporting NAND, NOR, SRAM, and OneNAND - enables direct attachment of legacy industrial memory devices. |
| PRU0_PRU1_UART0_RXD / PRU0_PRU1_UART0_TXD / PRU0_PRU1_GPMC_AD0 | PRU-ICSS I/O pins | Multiplexed signals for real-time protocol offload - allows PRU firmware to implement custom serial, GPIO, or bit-banged industrial interfaces. |
Key Features
| Feature | Design Value |
|---|---|
| Heterogeneous Processing | Arm A15 + dual C66x DSP + dual Cortex-M4 + PRU-ICSS - enables separation of control, algorithm, real-time, and protocol layers without software complexity. |
| 4K Video Pipeline | IVA-HD + VPE + HDMI 1.4a encoder - delivers full-HD (1920×1080p60) and 4K@15fps video output directly from SoC, eliminating need for external video processors. |
| Industrial Real-Time I/O | Dual PRU-ICSS with 2× dual-core RISC engines and dedicated local memory - supports deterministic sub-microsecond response for EtherCAT, PROFINET, and time-sensitive networking. |
| Hardware Security | Secure boot with eFuse-based key programming, AES/SHA2 crypto accelerators, and TrustZone® TEE - satisfies IEC 62443-3-3 SL2 and NIST SP 800-193 requirements for secure firmware updates. |
| Scalable Connectivity | PCIe Gen2, SATA Gen2, dual Gigabit Ethernet, USB 3.0/2.0, and 4× McSPI - consolidates high-bandwidth storage, wired/wireless backhaul, and sensor/actuator interfaces into single chip. |
Applications
| Industrial HMI Gateway | Machine Vision Edge Node |
|---|---|
Use Scenario: Embedded panel PC in factory automation controlling PLCs, reading sensors, and rendering real-time dashboards with video feed. IC Role / Device Role / Timing Role: Central applications processor executing Linux, managing multi-touch UI, decoding camera streams via CSI2, and driving HDMI display output. Use Value: Single-chip integration of Arm A15, C66x DSP, VPE, and HDMI encoder eliminates external video and graphics chips - reducing BOM cost and board area by >35%. |
Use Scenario: Smart camera system performing real-time defect detection on production line using neural network inference and high-resolution image capture. IC Role / Device Role / Timing Role: Host for vision algorithms on C66x DSP and Arm A15, with MIPI CSI-2 input, VPE preprocessing, and BB2D-accelerated image scaling/compositing. Use Value: On-chip VPE and BB2D reduce CPU load by 40% during image preprocessing, enabling sustained 60 fps 1080p analysis without thermal throttling. |
| Secure Industrial Gateway | Multi-Protocol Field Controller |
Use Scenario: Secure edge gateway aggregating Modbus, CAN, and Ethernet/IP data for cloud upload with encrypted TLS tunnel and firmware signing verification. IC Role / Device Role / Timing Role: Root-of-trust anchor with secure boot, crypto acceleration, and firewall-isolated network stacks running on Arm A15 and M4 coprocessors. Use Value: Hardware-enforced secure boot and AES-256/SHA2-512 acceleration cut OTA update verification time by 60% versus software-only implementations. |
Use Scenario: Programmable logic controller supporting EtherCAT master, PROFINET device, and CANopen slave simultaneously on same hardware platform. IC Role / Device Role / Timing Role: Dual PRU-ICSS subsystems independently executing protocol stacks with cycle-accurate timing, isolated from main OS via TrustZone®. Use Value: Deterministic <1 µs jitter on EtherCAT sync outputs enables precise motion control synchronization across 32 axes without external timing hardware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar high-performance industrial processor applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM5716BABCXASR | Omits IVA-HD, HDMI, VOUT1–3, SGX544 GPU, and VIP - no 4K video or 3D graphics capability; identical CPU/DSP/M4/PRU-ICSS core count and peripheral set otherwise. | Targeted at non-video industrial control where cost reduction outweighs multimedia features; cannot replace AM5718BABCXASR in vision or HMI applications. | Select AM5716BABCXASR only when video processing, HDMI output, or GPU acceleration are unnecessary - reduces unit cost by ~18% with identical real-time and security capabilities. |
| AM6548ABZDNA | Newer 16nm process, quad-core Arm Cortex-A53, dual-core Cortex-R5F safety MCU, enhanced PRU-ICSS, but no C66x DSP or IVA-HD; supports functional safety (ISO 26262 ASIL-B). | Designed for automotive and safety-critical industrial systems requiring ASIL-B compliance; lacks legacy DSP algorithm compatibility and 4K video decode. | Choose AM6548ABZDNA for new designs requiring functional safety certification or higher CPU throughput; retain AM5718BABCXASR for existing C66x-based vision codebases or 4K video requirements. |
Compared with AM5716BABCXASR, AM5718BABCXASR adds verified 4K video processing and HDMI output at identical real-time and security capability; compared with AM6548ABZDNA, it retains C66x DSP compatibility and IVA-HD but lacks ASIL-B certification and newer safety features.
Availability
AM5718BABCXASR is available at Aetrix Electronics and suitable for industrial HMI gateways, machine vision edge nodes, secure industrial gateways, and multi-protocol field controllers requiring stable component supply across extended product lifecycles.
Supply support for AM5718BABCXASR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets since 1930.
The AM571x Sitara™ processor family targets high-performance embedded applications demanding heterogeneous processing, real-time I/O, and hardware security - specifically designed for industrial HMIs, vision systems, and protocol gateways requiring long-term availability and AEC-Q100 qualification.
FAQ
What is the maximum DDR3 speed supported by AM5718BABCXASR?
The AM5718BABCXASR supports DDR3/DDR3L up to 1333 MT/s (667 MHz) across a single chip select, with capacity up to 2GB. This is confirmed in Section 1.1 Features and Table 5-10 of the SPRS957I datasheet for Silicon Revision 2.0 and 2.1. The EMIF module includes built-in calibration and supports JEDEC-compliant timing parameters including tRCD, tRP, and tRAS as specified in the DDR3 SDRAM datasheet.
Does AM5718BABCXASR support secure boot with customer-programmable keys?
Yes, AM5718BABCXASR supports hardware-enforced secure boot with customer-programmable keys via one-time programmable (OTP) eFuses, specifically enabled in Silicon Revision 2.1. This feature is documented in Section 1.1 Features and Section 5.8 (VPP Specifications for OTP eFuses) of SPRS957I Rev I. Keys are stored in secure memory and used to authenticate boot images before execution.
Can AM5718BABCXASR decode 4K video in real time?
Yes, AM5718BABCXASR supports 4K@15fps H.264 encode and decode through its integrated IVA-HD subsystem and Video Processing Engine (VPE), as explicitly stated in Section 1.1 Features of SPRS957I. Other codecs including VP8, MPEG-4, and VC-1 are supported up to 1080p60. This capability is silicon-verified and does not require external co-processors.
What industrial Ethernet protocols are supported by the PRU-ICSS in AM5718BABCXASR?
The dual PRU-ICSS subsystems in AM5718BABCXASR support EtherCAT®, PROFINET®, Ethernet/IP™, and POWERLINK™ through TI's certified protocol stacks. These are validated for real-time performance with sub-microsecond jitter, as confirmed in TI's AM571x Industrial Communications documentation and Section 1.1 Features listing "2x dual-core Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)."
Is AM5718BABCXASR qualified for automotive applications?
Yes, the AM571x Sitara™ processor family, including AM5718BABCXASR, is qualified according to the AEC-Q100 Standard for automotive grade 3 (–40°C to +125°C junction temperature), as stated in Section 1.3 Description of SPRS957I. This qualification covers reliability testing including HTOL, TC, and ESD - making it suitable for under-hood and infotainment applications requiring extended temperature operation.
AM5718BABCXASR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 760-BFBGA, FCBGA
- Series:
- Sitara™
- Packaging:
- Bulk
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A15
- Number of Cores/Bus Width:
- 1 Core, 32-Bit
- Speed:
- 1.5GHz
- Co-Processors/DSP:
- ARM® Cortex®-M4, BB2D, C66x, GPU, IVA
- RAM Controllers:
- DDR3, SRAM
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- HDMI, LCD
- Ethernet:
- 10/100/1000Mbps (1)
- SATA:
- SATA 3Gbps (1)
- USB:
- USB 2.0 + PHY (2), USB 3.0 + PHY (2)
- Voltage - I/O:
- 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 105°C (TJ)
- Grade:
- -
- Qualification:
- -
- Security Features:
- 3DES, AES, ARM TZ, Boot Security, Cryptography, MD5, SHA-1/2, TRNG
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 760-FCBGA (23x23)
- Additional Interfaces:
- CANbus, DMA, EBI/EMI, HDQ/1-Wire®, I2C, McASP, McSPI, MMC/SD/SDIO, PCIe, QSPI, UART
AM5718BABCXASR FAQ
1.How can I place an order for AM5718BABCXASR through Aetrix?
Please submit a Request for Quotation (RFQ) for AM5718BABCXASR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AM5718BABCXASR reliable?
The price and inventory of AM5718BABCXASR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AM5718BABCXASR is usually 5 days.
3.What payment methods are accepted for AM5718BABCXASR?
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4.How is shipping managed for AM5718BABCXASR?
AM5718BABCXASR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AM5718BABCXASR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AM5718BABCXASR?
For technical support, including AM5718BABCXASR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AM5718BABCXASR requirements.
6.How does Aetrix verify that AM5718BABCXASR is sourced from the original manufacturer or authorized distributors?
All AM5718BABCXASR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AM5718BABCXASR meets industry standards.
7.What is the process for return or replacement of AM5718BABCXASR?
All AM5718BABCXASR units undergo pre-shipment inspection (PSI). If there is an issue with AM5718BABCXASR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AM5718BABCXASR part is unused and in its original packaging.
Return procedure for AM5718BABCXASR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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