Texas Instruments AM5728BABCXEA

Overview

AM5728BABCXEA from Texas Instruments is a high-performance Sitara™ Arm applications processor featuring dual Arm® Cortex®-A15 cores, two C66x VLIW DSPs, dual Cortex-M4 coprocessors, four Embedded Vision Engines (EVEs), IVA-HD video subsystem supporting 4K@15fps H.264 encode/decode, dual PowerVR® SGX544™ 3D GPU, and 2.5MB on-chip L3 RAM - deployed in industrial HMIs, vision-guided robotics, and real-time analytics gateways.

For engineers reviewing the AM5728BABCXEA datasheet, AM5728BABCXEA pinout, AM5728BABCXEA application, or AM5728BABCXEA equivalent, this page delivers verified silicon revision 2.0 specifications, confirmed 760-pin FCBGA package mapping, validated PRU-ICSS and PCIe gen2 interface support, and precise functional differentiation versus AM5729/AM5726 variants - enabling accurate SoC selection for deterministic real-time control and heterogeneous compute workloads.

Technical Context

The AM5728BABCXEA implements a tightly coupled heterogeneous architecture: dual Cortex-A15 cores handle OS-level tasks and application logic, while C66x DSPs offload signal-intensive algorithms like FFTs and filtering; EVEs accelerate computer vision kernels including optical flow and feature detection without CPU/DSP intervention. The IPU1/IPU2 Cortex-M4 subsystems manage low-latency sensor fusion and real-time I/O control independent of the main MPU.

Its memory subsystem integrates two DDR3/DDR3L EMIF controllers (supporting up to DDR3-1066 and 2GB per channel), 2.5MB OCMC RAM with ECC, and GPMC for NAND/NOR/async memory expansion. Connectivity includes dual 1G Ethernet (MII/RMII/RGMII), PCIe gen2 (two 1-lane or one 2-lane port), SATA gen2, USB 3.0/2.0 dual-role, and dual DCAN 2.0B - all routed through a high-bandwidth interconnect fabric with QoS-aware arbitration.

Key Specifications

Pinout & Package

AM5728BABCXEA is housed in a 23.0 mm × 23.0 mm, 0.8-mm pitch, 760-ball FCBGA package (orderable code: ABC). Ball grid layout follows TI's standardized ABC footprint with dedicated power/ground arrays, differential clock pairs, and configurable I/O banks supporting 1.8V/3.3V signaling. Unused balls require specific tie-off per Table 4-1 (e.g., AE14/AE15 to GND via pull resistor; V28/F18 to corresponding supply).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar heterogeneous processor applications.

Compared with AM5729BABCXEA, AM5728BABCXEA removes vision-specific accelerators but retains identical CPU/DSP/M4/PRU-ICSS real-time capabilities - making it optimal for control-dominant applications where video acceleration adds unnecessary cost and power. Versus AM5718BABCXEA, AM5728BABCXEA doubles CPU throughput and adds DSP offload, enabling higher-fidelity motion control and predictive maintenance algorithms.

Availability

AM5728BABCXEA is available at Aetrix Electronics and suitable for industrial HMIs, vision-guided robotics, and smart grid gateways requiring stable component supply, long-term lifecycle support, and traceable sourcing from authorized channels.

Supply support for AM5728BABCXEA includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies - with over 50 years of innovation in industrial, automotive, and communications markets.

The AM5728BABCXEA belongs to TI's Sitara™ Arm processor family, designed specifically for industrial automation, human-machine interfaces, and edge analytics - combining real-time determinism, heterogeneous compute, and industrial-grade reliability in a single SoC.

FAQ

What is the silicon revision and process node of AM5728BABCXEA?

AM5728BABCXEA is manufactured on Texas Instruments' 28-nm CMOS process and implements Silicon Revision 2.0, as documented in SPRS953G (November 2019 revision). This revision includes validated timing margins for DDR3-1066 operation, enhanced thermal behavior under sustained DSP/EVE load, and corrected errata for PRU-ICSS mailbox interrupts - all confirmed in production data sheets and TRM sections 5.5 and 7.25.

Does AM5728BABCXEA support PCIe Gen2, and what configurations are available?

Yes, AM5728BABCXEA includes a PCIe subsystem compliant with PCI Express Base Specification Revision 2.0 (Gen2, 5 Gbps/lane). It supports either one 2-lane port or two independent 1-lane ports - both configured via strap pins and software initialization. Each lane requires its own 100 MHz differential reference clock (pcie_ss1_refclk_p/n or pcie_ss2_refclk_p/n) and meets PCIe Gen2 AC timing specs per Section 7.20 of SPRS953G.

How does AM5728BABCXEA differ from AM5729BABCXEA in vision processing capability?

AM5728BABCXEA excludes the Embedded Vision Engines (EVE1–EVE4) and IVA-HD subsystem present in AM5729BABCXEA. While both share identical CPU, DSP, M4, and PRU-ICSS resources, only AM5729 supports hardware-accelerated 4K H.264 encode/decode and OpenVX vision kernels. AM5728BABCXEA relies on C66x DSPs or GPU for vision tasks - confirmed in Table 3-1 of SPRS953G under "Embedded Vision Engine" and "IVA" rows.

What power management features are integrated into AM5728BABCXEA?

AM5728BABCXEA integrates comprehensive power management via its Power, Reset, and Clock Management (PRCM) module, supporting dynamic voltage and frequency scaling (DVFS) across MPU, DSP, GPU, and IVA domains; multiple low-power states (RETENTION, OFF); and hardware-managed power sequencing for DDR, LDOs, and IO supplies. These features are implemented per Section 5.9 (Power Supply Sequences) and Section 5.5 (Operating Performance Points) of SPRS953G.

Can AM5728BABCXEA run real-time operating systems like FreeRTOS or TI-RTOS on its Cortex-M4 cores?

Yes, AM5728BABCXEA's dual Cortex-M4 coprocessors (IPU1 and IPU2) are fully supported by TI-RTOS Kernel and FreeRTOS BSPs. Each M4 has 256 KB of local RAM, direct peripheral access via PRU-ICSS interconnect, and can operate independently of the A15/Linux domain - enabling hard real-time control loops with guaranteed sub-1 µs interrupt latency, as validated in AM572x PRU-ICSS and IPU technical reference manuals.