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Texas Instruments AM62A74AUMSIAMBRQ1
- Part No.:
- AM62A74AUMSIAMBRQ1
- Manufacturer:
- Texas Instruments
- Category:
- Microprocessors
- Package:
- 484-BFBGA, FCBGA
- Datasheet:
-
AM62A74AUMSIAMBRQ1.pdf
- Description:
- 2 TOPS VISION SOC WITH RGB-IR IS
- Quantity:
- Payment:
- Shipping:
Inventory:3,064
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Product details
Overview
AM62A74AUMSIAMBRQ1 from Texas Instruments is an automotive-grade heterogeneous Arm® processor featuring quad-core Cortex-A53 (up to 1.4GHz), dual Cortex-R5F MCUs (800MHz each), C7x-based Deep Learning Accelerator (2 TOPS @ 1.0GHz), VPAC with 5MP@60fps ISP, and integrated 3-port Gigabit Ethernet switch with TSN support. It targets driver monitoring systems, eMirrors, and machine vision cameras requiring real-time analytics and functional safety.
For engineers reviewing the AM62A74AUMSIAMBRQ1 datasheet, AM62A74AUMSIAMBRQ1 pinout, AM62A74AUMSIAMBRQ1 application, or AM62A74AUMSIAMBRQ1 equivalent, this page delivers verified specifications, validated pin functions, automotive safety context (ASIL B hardware, ASIL D systematic capability), and confirmed alternative parts for DMS/OMS and vision-ECU designs.
Technical Context
The AM62A74AUMSIAMBRQ1 implements a heterogeneous architecture with three independent processing domains: Application (Cortex-A53 cluster with 512KB L2 SECDED ECC), MCU Channel (Cortex-R5F with 512KB SRAM + TCM, all SECDED ECC), and Device Management (Cortex-R5F with 64KB TCM + 64KB SRAM, SECDED ECC). Its VPAC supports 12-bit RGB-IR input, WDR, LDC, and up to 315MPixel/s throughput, while the C7x MMA delivers 2TOPS at 1.0GHz with 1.25MB L2 SRAM (SECDED ECC).
Functional safety is architected via dual R5F isolation, safety monitor (ESM), error-correcting memories across all subsystems, and dedicated safety firmware space (176KB OCRAM). Security includes HSM with user-programmable core, TrustZone-based TEE, AES/SHA/PKA acceleration, and secure boot with RoT backup key switching - all qualified per AEC-Q100 Grade 2 (–40°C to +105°C) and ISO 26262 ASIL D-targeted development process.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Quad 64-bit Arm Cortex-A53 @ up to 1.4GHz; dual Arm Cortex-R5F @ up to 800MHz (MCU Channel + Device Management) |
| Deep Learning Performance | 2 TOPS (8-bit) via C7x MMA accelerator at 1.0GHz, backed by 1.25MB L2 SRAM with SECDED ECC |
| Vision Processing | VPAC with ISP supporting 5MP @ 60fps, 12-bit RGB-IR, 16-bit RAW, WDR, LDC, and 315MPixel/s throughput |
| Memory Interface | LPDDR4 subsystem: 32-bit bus with inline ECC, up to 3733MT/s, 8GB addressable range |
| Networking | Integrated 3-port Gigabit Ethernet switch (2 external RGMII/RMII ports) with IEEE 1588, TSN, and hardware checksum offload |
| Automotive Qualification | AEC-Q100 Grade 2 (–40°C to +105°C); ISO 26262 ASIL D-targeted systematic capability, ASIL B-targeted hardware integrity |
| Security Features | HSM with programmable core, TrustZone TEE, AES-128/192/256, SHA2-224/256/384/512, PKA, DRBG, RPMB, and secure debug control |
| Package | 484-pin FCBGA (AMB) or FCCSP (ANF), 18mm × 18mm, 0.8mm pitch, 16-nm FinFET technology |
Pinout & Package
AM62A74AUMSIAMBRQ1 is packaged in a 484-ball FCBGA (AMB) or FCCSP (ANF), both 18mm × 18mm with 0.8mm pitch. The package supports full-array ball layout optimized for automotive thermal and signal integrity requirements, including dedicated DDR, OSPI, CSI-2, and Ethernet routing zones.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DDR0_DQ0–DDR0_DQ31 | LPDDR4 Data Bus | 32-bit bidirectional data interface with per-byte DM and DQS strobes; supports inline ECC and 3733MT/s operation |
| CSI0_RXP0–CSI0_RXN3 | CSI-2 Receiver Differential Pairs | Four-lane MIPI D-PHY v1.2 receiver supporting up to 2.5Gbps/lane, ECC/CRC on RAM, and direct-to-DDR DMA |
| RGMII1_TD0–RGMII1_RD3 | Gigabit Ethernet PHY Interface | First RGMII port with TX/RX clock/data lanes; supports 10/100/1000BASE-T, IEEE 1588 timestamping, and TSN traffic shaping |
| OSPI0_D0–OSPI0_D7 | Octal-SPI Flash Interface | 8-bit bidirectional data bus supporting XIP mode, DDR/SDR, serial NAND/NOR, and on-the-fly encryption |
| MCAN0_TX/MCAN0_RX | CAN-FD Transceiver Interface | Dual CAN-FD channels (3 total) supporting up to 8Mbps, 64-byte payloads, and parity/ECC-protected message RAM |
| VDD_CORE / VDDS_DDR / VDDA_PLL0 | Power Supply Domains | Separate regulated rails for core logic (0.75V), DDR I/O (1.1V), and PLL analog (1.8V); each with dedicated decoupling and monitoring |
Key Features
| Feature | Design Value |
|---|---|
| Functional Safety Architecture | Dual isolated Cortex-R5F cores, ESM watchdog, SECDED ECC on all on-chip RAM (including 1.25MB C7x L2), and ASIL D-targeted development process |
| Vision Analytics Pipeline | VPAC with configurable ISP enabling simultaneous RGB-IR processing, multi-scalar scaling (MSC), VISS, and 315MPixel/s throughput for DMS/OMS |
| Secure Boot Enforcement | Hardware-rooted RoT with backup key switching, anti-rollback, IP protection, and HSM-managed cryptographic key lifecycle |
| Industrial Networking Integration | 3-port Ethernet switch with TSN (IEEE 802.1AS/1Qbv), hardware packet classification (512 entries), and CPU interrupt pacing for deterministic latency |
| Low-Power Vision Processing | DeepSleep (suspend-to-RAM) and MCU-only modes with partial IO wakeup (CAN/GPIO/UART); dynamic frequency scaling for Cortex-A53 |
| Multi-Modal Sensor Support | CSI-2 (4-lane), OSPI (XIP flash), GPMC (NAND/NOR), and 3× MMC/SD interfaces enable flexible camera, storage, and peripheral expansion |
Applications
| Driver Monitoring System (DMS) | eMirror / Camera Mirror System (CMS) |
|---|---|
Use Scenario: Real-time facial landmark detection, gaze tracking, and drowsiness analysis in automotive cabins using infrared and visible-light cameras. IC Role / Device Role / Timing Role: Primary vision SoC executing Linux-based AI inference (YOLOv5, ResNet) on C7x MMA while VPAC handles synchronized RGB-IR ISP preprocessing. Use Value: 2TOPS DL acceleration enables sub-50ms inference latency at 60fps; ASIL D-targeted safety architecture satisfies ISO 26262 system-level requirements. |
Use Scenario: Replacing physical rearview mirrors with low-latency video streams from multiple wide-angle cameras, displayed on digital dashboards. IC Role / Device Role / Timing Role: Central video processor managing up to 5MP@60fps camera inputs, HEVC/H.265 encoding, and DPI display output with freeze-frame detection. Use Value: Integrated 2048×1080 DPI controller and hardware video codec reduce BOM cost; TSN-enabled Ethernet ensures deterministic camera-to-display timing. |
| Machine Vision Camera | Autonomous Mobile Robot (AMR) Vision Node |
Use Scenario: High-resolution barcode scanning and object recognition in logistics automation, operating under variable lighting and motion blur. IC Role / Device Role / Timing Role: Vision-optimized SoC running embedded Linux with VPAC ISP correcting lens distortion (LDC) and WDR, feeding C7x for CNN-based decoding. Use Value: 12-bit RGB-IR support and 16-bit RAW input enable robust decoding in low-light; 315MPixel/s throughput sustains 60fps at 4K resolution. |
Use Scenario: On-robot perception node performing SLAM, obstacle avoidance, and occupancy mapping using stereo or time-of-flight cameras. IC Role / Device Role / Timing Role: Real-time vision co-processor interfacing with ROS 2 via Ethernet TSN, offloading feature extraction and neural inference from host MCU. Use Value: Dual Cortex-R5F MCUs handle safety-critical motion control loops while Cortex-A53 runs perception stack; CAN-FD connects to motor drivers and sensors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar vision-SoC applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AM62A34AUMSIAMBRQ1 | Dual-core Cortex-A53 (vs. quad), no C7x MMA (0 TOPS), same VPAC/ISP, identical package and pinout | Suitable for cost-sensitive DMS with lower algorithm complexity; lacks 2TOPS DL acceleration for high-res CNNs | Select when DL inference load fits within CPU-only execution and ASIL D systematic capability is retained |
| AM625SKABAAIA | Non-automotive grade (commercial temp), dual-display DPI, 3D GPU, no functional safety certification or ASIL targeting | Targeted at human-machine interface (HMI) with GUI rendering; lacks VPAC bandwidth and safety features for DMS/CMS | Choose only for non-safety-critical industrial HMIs where dual HD display and graphics outweigh vision acceleration needs |
Compared with AM62A34AUMSIAMBRQ1, AM62A74AUMSIAMBRQ1 adds 2TOPS DL acceleration and quad-core A53 for higher AI throughput, while AM625SKABAAIA trades safety and vision performance for graphics and dual-display support - making AM62A74AUMSIAMBRQ1 uniquely suited for certified automotive vision ECUs.
Availability
AM62A74AUMSIAMBRQ1 is available at Aetrix Electronics and suitable for Driver Monitoring Systems (DMS), eMirror/Camera Mirror Systems (CMS), Machine Vision Cameras, and Autonomous Mobile Robot (AMR) vision nodes requiring stable component supply, automotive qualification, and long-term lifecycle support.
Supply support for AM62A74AUMSIAMBRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in automotive processors, power management, and signal chain solutions.
The AM62A74AUMSIAMBRQ1 belongs to TI's Sitara™ automotive-grade processor family, designed specifically for cost-optimized, safety-certifiable vision and AI edge applications in driver/in-cabin monitoring, eMirrors, and industrial robotics.
FAQ
What is the functional safety qualification status of AM62A74AUMSIAMBRQ1?
AM62A74AUMSIAMBRQ1 is AEC-Q100 Grade 2 qualified (–40°C to +105°C) and developed to ISO 26262 ASIL D-targeted systematic capability with ASIL B-targeted hardware integrity. TÜV SÜD certification is planned. Safety documentation, including FMEDA and safety manuals, is available to support system-level ASIL decomposition and integration into automotive ECUs.
Does AM62A74AUMSIAMBRQ1 support MIPI CSI-2 camera interfaces?
Yes, AM62A74AUMSIAMBRQ1 integrates a single 4-lane MIPI CSI-2 v1.3 receiver compliant with D-PHY 1.2, supporting data rates up to 2.5Gbps per lane, virtual channel support (up to 16), ECC/CRC verification on internal RAM, and direct DMA streaming to DDR memory - essential for multi-camera DMS/OMS systems.
What deep learning acceleration does AM62A74AUMSIAMBRQ1 provide?
AM62A74AUMSIAMBRQ1 includes a C7x-based Deep Learning Accelerator with Matrix Multiply Accelerator (MMA) delivering up to 2 TOPS (8-bit) at 1.0GHz, backed by 1.25MB L2 SRAM with SECDED ECC. It supports common frameworks (TensorFlow Lite, ONNX) via TI's Processor SDK and supports INT8/FP16 precision for vision inference workloads.
Can AM62A74AUMSIAMBRQ1 run Linux and real-time tasks simultaneously?
Yes, AM62A74AUMSIAMBRQ1 supports concurrent execution: Linux runs on the quad-core Cortex-A53 cluster for application processing, while safety-critical real-time tasks execute on the isolated Cortex-R5F MCU Channel (with 512KB SRAM and SECDED ECC) and Device Management R5F core - enabling mixed-criticality systems without hypervisor overhead.
What display interfaces does AM62A74AUMSIAMBRQ1 support?
AM62A74AUMSIAMBRQ1 supports a single DPI (Display Parallel Interface) output with 24-bit RGB, up to 2048×1080 @ 60fps and 165MHz pixel clock. It includes safety features such as freeze-frame detection and MISR data checking, but does not support HDMI, LVDS, or dual-display configurations - those require AM625 or AM62P variants.
AM62A74AUMSIAMBRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Package/Case:
- 484-BFBGA, FCBGA
- Series:
- Sitara™
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Core Processor:
- ARM® Cortex®-A53
- Number of Cores/Bus Width:
- 4 Core, 64-Bit
- Speed:
- 1.4GHz
- Co-Processors/DSP:
- ARM® Cortex®-R5F
- RAM Controllers:
- DDR4, LPDDR4
- Graphics Acceleration:
- Yes
- Display & Interface Controllers:
- MIPI-CSI
- Ethernet:
- 10/100/1000Mbps (2)
- SATA:
- -
- USB:
- USB 2.0 (2)
- Voltage - I/O:
- 1.1V, 1.2V, 1.8V, 3.3V
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- Automotive
- Qualification:
- -
- Security Features:
- AES, ARM TZ, Cryptography, DRBG, ECC, MD5, PKA, Random Number Generator, RSA, Secure Boot, SHA2, SMS
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 484-FCBGA (18x18)
- Additional Interfaces:
- DMA, GPIO, I2C, I2S, MMC/SD, QSPI, SPDIF, SPI, TDM, UART/USART
AM62A74AUMSIAMBRQ1 FAQ
1.How can I place an order for AM62A74AUMSIAMBRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for AM62A74AUMSIAMBRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AM62A74AUMSIAMBRQ1 reliable?
The price and inventory of AM62A74AUMSIAMBRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AM62A74AUMSIAMBRQ1 is usually 5 days.
3.What payment methods are accepted for AM62A74AUMSIAMBRQ1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AM62A74AUMSIAMBRQ1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AM62A74AUMSIAMBRQ1?
AM62A74AUMSIAMBRQ1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AM62A74AUMSIAMBRQ1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AM62A74AUMSIAMBRQ1?
For technical support, including AM62A74AUMSIAMBRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AM62A74AUMSIAMBRQ1 requirements.
6.How does Aetrix verify that AM62A74AUMSIAMBRQ1 is sourced from the original manufacturer or authorized distributors?
All AM62A74AUMSIAMBRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AM62A74AUMSIAMBRQ1 meets industry standards.
7.What is the process for return or replacement of AM62A74AUMSIAMBRQ1?
All AM62A74AUMSIAMBRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with AM62A74AUMSIAMBRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AM62A74AUMSIAMBRQ1 part is unused and in its original packaging.
Return procedure for AM62A74AUMSIAMBRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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