Alpha & Omega Semiconductor Inc. AOZ1390DI-02
- Part No.:
- AOZ1390DI-02
- Manufacturer:
- Alpha & Omega Semiconductor Inc.
- Package:
- 14-VFDFN Exposed Pad
- Datasheet:
-
AOZ1390DI-02.pdf
- Description:
- 23V IDEAL DIODE SINK SWITCH LATC
- Quantity:
- Payment:

- Shipping:

Inventory:2,984
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AOZ1390DI-02 from Alpha & Omega Semiconductor is a latch-off ideal diode protection switch for USB PD multi-port power ORing, providing reverse current blocking, 18 mΩ typical RON, 3.3 V–23 V input range, and integrated LPS fault coordination across ports. It operates in high-side configuration with thermal shutdown, over-voltage, and short-circuit protection.
For engineers reviewing the AOZ1390DI-02 datasheet, pinout, applications, or equivalent options, key selection considerations include latch-off fault response (vs. auto-restart), 2.5 s LPSB debounce timing, VIN discharge capability, IDTRCB regulation at 35 mV, and DFN3.5×3-14L thermal pad layout requirements.
Technical Context
The AOZ1390DI-02 implements back-to-back N-channel MOSFETs with gate drive and charge pump to enable true reverse-current blocking (IDTRCB) and programmable soft-start via external CSS capacitor. Its control logic enforces latch-off behavior on OVP, TSD, and startup SCP-requiring EN toggle or VIN cycle for recovery.
It integrates dedicated LPS detection (6.3 V threshold, 2.5 s blanking) that asserts LPSB low when EN = 0 V and VIN exceeds threshold, enabling coordinated shutdown of other ports via DISB. FLTB provides open-drain fault reporting for thermal, over-voltage, and short-circuit events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 3.3 V to 23 V - supports full USB PD voltage range with 30 V absolute max rating on VIN/VOUT. |
| RON (Typical) | 18 mΩ at 20 V, IOUT > 2.25 A - minimizes conduction loss and thermal rise under 8 A continuous load. |
| Fault Response Mode | Latch-off - disables power switch permanently until EN toggled or VIN cycled; no automatic retries. |
| IDTRCB Regulation | 35 mV VIN–VOUT drop - actively maintains reverse-current blocking by modulating gate drive below this threshold. |
| LPSB Detection Threshold | 6.3 V with 150 mV hysteresis - triggers coordinated port shutdown when disabled port sees overvoltage, preventing bus energization from faulty sources. |
| Soft-Start Control | Externally programmable via CSS capacitor - sets 10%–90% VOUT ramp time; enables inrush current management for ≥10 µF COUT. |
| Thermal Shutdown | 140 °C with no hysteresis - latches off immediately; requires external reset, unlike AOZ1390DI-01's auto-restart. |
| Startup SCP Recovery | 4 retry attempts at 2 ms intervals - final latch-off if short persists; prevents repeated stress during capacitive inrush. |
Pinout & Package
AOZ1390DI-02 is housed in a thermally enhanced DFN3.5 mm × 3 mm, 14-lead package with exposed thermal pad (EXP) tied to internal drain node. The EXP pad must be soldered to isolated copper thermal planes using multiple vias for junction-to-board thermal resistance of 2 °C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN (Pins 13,14) | Power input terminal | Accepts 3.3–23 V supply; internally discharges to GND when EN = low (2.5 mA sink). |
| VOUT (Pins 1,2) | Power output terminal | Delivers regulated output; supports up to 8 A continuous; rated 30 V abs max. |
| EN (Pin 6) | Enable control input | Active-high logic (1.4 V threshold); toggling resets latch-off faults. |
| FLTB (Pin 5) | Fault indicator output | Open-drain, active-low signal flagging OVP, TSD, or startup SCP. |
| LPSB (Pin 9) | Limited Power Source fault output | Open-drain, active-low output asserting after 2.5 s VIN > 6.3 V while EN = 0 V. |
| DISB (Pin 10) | Disable-bar input | Pull-up biased (10 µA); falling edge forces immediate MOSFET turn-off while IC remains powered. |
| SS (Pin 8) | Soft-start timing node | Connect external capacitor (CSS) to GND to set VOUT ramp time; controls inrush into COUT. |
| GND (Pin 7) | Ground reference | Primary return path; must connect directly to solid ground plane without narrow traces. |
| CAP (Pin 4) | Internal bias capacitor node | Requires 1 nF capacitor to GND; no external loading permitted. |
| NC (Pin 3), DNC (Pins 11,12) | No-connect / do-not-connect | Pin 3 is unconnected; Pins 11–12 are internally tied to common drain node - no external connection allowed. |
Key Features
| Feature | Design Value |
|---|---|
| True Reverse Current Blocking (IDTRCB) | Maintains ≤35 mV VIN–VOUT differential to prevent reverse flow under all load conditions, including light/no-load. |
| Limited Power Source (LPS) Coordination | Enables multi-port systems to isolate faulty inputs via LPSB→DISB interconnection, eliminating uncontrolled power flow from damaged ports. |
| Latch-Off Fault Recovery | Guarantees system stability by preventing uncontrolled restarts during persistent OVP, TSD, or SCP - requires explicit operator or controller intervention. |
| Programmable Soft-Start | External CSS capacitor sets controlled VOUT ramp (ms-scale), limiting inrush into large output capacitances without sacrificing startup speed. |
| VIN Discharge Function | 2.5 mA internal sink activates when EN = low and VIN falls below 4.4 V, discharging VIN to <0.8 V within 1 s to meet safety standards. |
| Robust SOA Handling | Supports 20 A pulsed current (10 ms, 2% duty cycle) and linear-mode soft-start power dissipation up to 120 W, validated by SOA curve. |
Applications
| USB PD Multi-Port Power ORing | High-End Laptop Type-C Power Input |
|---|---|
Use Scenario: Multiple Type-C ports share a single VBUS rail; one port may develop internal short while others remain functional. IC Role / Device Role / Timing Role: AOZ1390DI-02 acts as high-side ideal diode per port, enforcing LPS coordination so a shorted port pulls LPSB low, forcing DISB-driven shutdown of all other ports. Use Value: Prevents uncontrolled 20 V/5 A power flow from healthy ports into a shorted port, avoiding thermal runaway and system-level damage. |
Use Scenario: Ultrabook with dual USB-C ports accepting up to 100 W PD input; peak CPU/GPU loads demand transient currents >10 A. IC Role / Device Role / Timing Role: AOZ1390DI-02 serves as primary input protection switch with 18 mΩ RON, enabling efficient delivery of sustained 8 A and 20 A pulses without derating. Use Value: Maintains stable VBUS rail during 2 ms CPU boost events while suppressing reverse current from battery or secondary rails. |
| Smartphone/Tablet Dual-Charger ORing | Industrial USB-C Docking Station |
Use Scenario: Tablet accepts charging from either wall adapter or PC host; both sources must be isolated when inactive. IC Role / Device Role / Timing Role: AOZ1390DI-02 provides bidirectional isolation with IDTRCB, ensuring no backfeed from higher-voltage source to lower-voltage source. Use Value: Eliminates need for external Schottky diodes, reducing forward drop loss and PCB area while guaranteeing zero reverse leakage. |
Use Scenario: Docking station with three Type-C ports powering laptop, monitor, and peripherals; one port sustains overvoltage due to cable fault. IC Role / Device Role / Timing Role: AOZ1390DI-02 on each port monitors VIN during disable state; LPSB assertion disables all ports via shared DISB net. Use Value: Achieves fail-safe bus de-energization without firmware involvement, meeting industrial reliability and safety certification requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar ideal diode protection applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AOZ1390DI-01 | Auto-restart fault response (64 ms interval) vs. latch-off; includes 30 °C TSD hysteresis; VOVP hysteresis = 300 mV. | Suitable for consumer devices where automatic recovery from transient faults is preferred over guaranteed manual reset. | Select AOZ1390DI-01 only if system firmware cannot manage latch-off reset and transient OVP/TSD events are expected. |
| TPS2410RGER | Adjustable OVP threshold (1.215 V reference), no integrated LPS function, 22 mΩ RON, SOIC-16 package. | Used in legacy industrial ORing designs requiring field-programmable thresholds and through-hole compatibility. | Choose TPS2410RGER only when LPS coordination is unnecessary and board space allows larger SOIC footprint. |
Compared with AOZ1390DI-01 and TPS2410RGER, AOZ1390DI-02 uniquely combines latch-off safety enforcement, integrated LPS fault signaling, and compact DFN3.5×3-14L packaging - making it optimal for certified USB PD multi-port systems where deterministic fault containment is mandatory.
Availability
AOZ1390DI-02 is available at Aetrix Electronics and suitable for USB PD multi-port ORing, high-end laptop power input, smartphone dual-charger isolation, and industrial docking station designs requiring stable component supply with guaranteed RoHS-compliant sourcing.
Supply support for AOZ1390DI-02 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Alpha & Omega Semiconductor (AOS) is a fabless power semiconductor company specializing in high-efficiency MOSFETs, power ICs, and advanced packaging for power management applications.
The AOZ1390DI product line delivers ECPower™ ideal diode switches optimized for USB Type-C PD systems, emphasizing reverse-current blocking, multi-port coordination, and robust fault containment in thermally constrained form factors.
FAQ
What fault conditions cause AOZ1390DI-02 to latch off permanently?
AOZ1390DI-02 latches off upon detection of over-voltage (VIN > 24 V), thermal shutdown (TJ ≥ 140 °C), or startup short-circuit (SCP) after four 2 ms retry attempts. Unlike AOZ1390DI-01, it does not auto-restart. Recovery requires toggling the EN pin or cycling VIN - ensuring no uncontrolled re-engagement during persistent faults. This behavior is hard-coded in the AOZ1390DI-02 silicon revision.
How does AOZ1390DI-02 implement Limited Power Source (LPS) protection?
AOZ1390DI-02 monitors VIN while EN = 0 V; if VIN exceeds 6.3 V for 2.5 s, LPSB pulls low. This signal can drive DISB pins of other AOZ1390DI-02 devices in multi-port systems, forcing coordinated shutdown. LPSB clears only when VIN drops below 6.15 V or EN is asserted - not when DISB returns high. AOZ1390DI-02 uses this to prevent uncontrolled power flow from a shorted port into the shared VOUT bus.
Can AOZ1390DI-02 replace AOZ1390DI-01 in an existing design?
No direct replacement is recommended without validation. AOZ1390DI-02's latch-off behavior changes system-level fault handling: OVP, TSD, and SCP now require manual or controller-initiated reset instead of auto-restart. Layout, thermal management, and firmware must be updated to accommodate the absence of automatic recovery cycles. Pinout and electrical specs are identical, but fault-state persistence alters system safety architecture.
What is the purpose of the CAP pin on AOZ1390DI-02?
The CAP pin on AOZ1390DI-02 connects to an internal bias network and requires a 1 nF capacitor to GND for stable operation. No external load or signal routing is permitted. This capacitor stabilizes internal charge pump and gate driver references; omitting it causes erratic switching, false fault flags, or failure to regulate IDTRCB. It is not a filter or bypass node - its sole function is internal bias integrity.
How does AOZ1390DI-02 achieve True Reverse Current Blocking (IDTRCB)?
AOZ1390DI-02 achieves IDTRCB by continuously regulating VOUT to maintain a 35 mV drop below VIN. When VOUT approaches or exceeds VIN - due to backfeed from batteries, secondary supplies, or parasitic coupling - the gate driver reduces conduction until the MOSFETs fully block. This occurs in <40 µs, verified in Figure 10 of the datasheet, and functions independently of load current or EN state, ensuring zero reverse current under all operating conditions.
AOZ1390DI-02 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Alpha & Omega Semiconductor Inc.
- Package/Case:
- 14-VFDFN Exposed Pad
- Series:
- -
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Switch Type:
- General Purpose
- Number of Outputs:
- 1
- Ratio - Input:Output:
- 1:1
- Output Configuration:
- High Side
- Output Type:
- N-Channel
- Interface:
- On/Off
- Voltage - Load:
- 3.3V ~ 23V
- Voltage - Supply (Vcc/Vdd):
- 3.3V ~ 23V
- Current - Output (Max):
- 8A
- Rds On (Typ):
- 19mOhm
- Input Type:
- Non-Inverting
- Features:
- Slew Rate Controlled, Status Flag
- Fault Protection:
- Current Limiting (Adjustable), Over Temperature, Over Voltage, Reverse Current, UVLO
- Operating Temperature:
- -40°C ~ 125°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-DFN (3.5x3)
AOZ1390DI-02 FAQ
1.How can I place an order for AOZ1390DI-02 through Aetrix?
Please submit a Request for Quotation (RFQ) for AOZ1390DI-02 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AOZ1390DI-02 reliable?
The price and inventory of AOZ1390DI-02 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AOZ1390DI-02 is usually 5 days.
3.What payment methods are accepted for AOZ1390DI-02?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AOZ1390DI-02 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AOZ1390DI-02?
AOZ1390DI-02 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AOZ1390DI-02 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AOZ1390DI-02?
For technical support, including AOZ1390DI-02 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AOZ1390DI-02 requirements.
6.How does Aetrix verify that AOZ1390DI-02 is sourced from the original manufacturer or authorized distributors?
All AOZ1390DI-02 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AOZ1390DI-02 meets industry standards.
7.What is the process for return or replacement of AOZ1390DI-02?
All AOZ1390DI-02 units undergo pre-shipment inspection (PSI). If there is an issue with AOZ1390DI-02, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AOZ1390DI-02 part is unused and in its original packaging.
Return procedure for AOZ1390DI-02:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AOZ1390DI-02 Tags

-
TPS22919DCKR
Texas Instruments

-
MIC2091-1YM5-TR
Microchip Technology

-
MIC2090-1YM5-TR
Microchip Technology

-
TPS22995RZFR
Texas Instruments

-
TPS22975DSGR
Texas Instruments

-
SIP32510DT-T1-GE3
Vishay Siliconix

-
ULN2003D1013TR
STMicroelectronics

-
MIC2005A-1YM5-TR
Microchip Technology

-
MIC2005A-1YM6-TR
Microchip Technology

-
TPS22916BYFPR
Texas Instruments

-
TPS22917DBVR
Texas Instruments
-
ULN2003APWR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
