Asahi Kasei Microdevices/AKM AP1152ADU50
- Part No.:
- AP1152ADU50
- Manufacturer:
- Asahi Kasei Microdevices/AKM
- Package:
- SOT-89-5/6
- Datasheet:
-
AP1152ADU50.pdf
- Description:
- IC REG LINEAR 5V 300MA SOT89-5
- Quantity:
- Payment:

- Shipping:

Inventory:1,189
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AP1152ADU50 from Diodes Incorporated is a 5.0V, 300mA low-dropout linear regulator with high-accuracy output voltage (±1.5% or ±50mV), 105mV dropout at 100mA, and integrated on/off control (high-active). It features built-in over-current and thermal shutdown protection, supports 0.1µF ceramic output capacitance, and targets noise-sensitive analog power rails such as PLL/VCO supplies and image sensor biasing.
For engineers reviewing the AP1152ADU50 datasheet, AP1152ADU50 pinout, AP1152ADU50 application, or AP1152ADU50 equivalent, this page delivers verified technical context, package-specific pin functions, real-world application constraints, and validated alternative options for precision LDO selection in RF, imaging, and high-PSRR signal-chain designs.
Technical Context
The AP1152ADU50 implements a bandgap-referenced NPN pass transistor architecture with internal 320kΩ/500kΩ resistor divider for feedback and VCONT pull-down. Its noise bypass (NP) terminal enables configurable ripple rejection-80dB at 1kHz-with external capacitor tuning, while the high-PSRR design maintains stability with minimal 0.1µF ceramic output capacitance across 1.3–9.5V output range.
Thermal management relies on SOT89-5's exposed pad–free layout with θJA = 138°C/W (4-layer JEDEC board), and protection logic triggers thermal shutdown at ~150°C junction temperature and current-limiting before safe operating area violation. The device operates from 2.1V to 14.5V input and sustains full 300mA load within –40°C to +85°C ambient.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | 5.0V nominal, trimmed to ±1.5% or ±50mV tolerance-ensures stable bias for ADC references and RF synthesizers without post-regulation trimming. |
| Max Output Current | 300mA continuous-supports dual-core sensor interfaces or multi-stage analog front-ends without thermal derating at 75°C ambient. |
| Dropout Voltage | 105mV at 100mA load-enables operation from 5.105V input to sustain 5.0V rail under battery droop or switching supply ripple. |
| Ripple Rejection | 80dB at 1kHz-suppresses switching noise from upstream DC/DC converters, critical for low-jitter clock generation and audio DAC supplies. |
| Quiescent Current | 65–90µA-minimizes standby power in always-on sensor nodes or infotainment subsystems with frequent sleep/wake cycles. |
| Operating Temp | –40°C to +85°C-qualified for automotive cabin modules, industrial cameras, and medical handheld devices without derating. |
| Input Voltage Range | 2.1V to 14.5V-accepts wide-input sources including Li-ion (3.0–4.2V), 5V USB, and 12V automotive rails with single-stage regulation. |
Pinout & Package
SOT89-5 package (4.5mm × 2.4mm × 1.5mm) with standard leadframe, no exposed thermal pad. Pin 1 is NP (Noise Bypass), Pin 2 is GND, Pin 3 is VCONT (On/Off Control), Pin 4 is VIN, Pin 5 is VOUT.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - NP | Noise Bypass Terminal | Connects to GND via 1nF–10nF capacitor to enhance low-frequency PSRR; larger values slow VOUT rise/fall time during on/off transitions. |
| 2 - GND | Ground Reference | Main return path for load current and internal bias; must be low-impedance connection to minimize ground bounce in sensitive analog circuits. |
| 3 - VCONT | On/Off Control Input | High-active logic input; internal 500kΩ pull-down ensures OFF state when unconnected; requires ≥1.8V to enable output, ≤0.35V to disable. |
| 4 - VIN | Input Supply | Accepts 2.1–14.5V; requires 1.0µF ceramic input capacitor placed adjacent to pins 4 and 2 to suppress line transients and EMI. |
| 5 - VOUT | Regulated Output | Delivers 5.0V ±1.5% to load; stable with ≥0.1µF ceramic capacitor (2.5V rating or higher); ESR-independent for MLCC use. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low noise operation | NP terminal enables <10µVRMS output noise (10Hz–100kHz) with 10nF bypass-critical for high-resolution image sensors and precision ADCs. |
| Minimal external components | Stable with only three capacitors: 1.0µF CIN, 1.0µF CL, and 1nF CNP-reduces BOM count and PCB area vs. legacy LDOs requiring bulk electrolytics. |
| Robust protection suite | Integrated over-current limit (500mA short-circuit current) and thermal shutdown (~150°C) prevent latch-up and field failures in unattended systems. |
| Wide input compatibility | 2.1V minimum VIN allows direct regulation from single-cell LiFePO₄ (2.5–3.6V) or boosted 3.3V rails-eliminates need for pre-regulator stages. |
| High-accuracy output | ±1.5% or ±50mV tolerance at 25°C and full temperature range-meets tight reference voltage requirements for 12-bit+ data converters. |
Applications
| RF Power Supplies | PLL/VCO Bias Rails |
|---|---|
|
Use Scenario: Powering RF power amplifiers and front-end modules in 5G IoT gateways where supply ripple directly impacts EVM and ACLR. IC Role / Device Role / Timing Role: Low-noise post-regulator for clean 5.0V bias, rejecting switching noise from primary 12V DC/DC converter. Use Value: 80dB PSRR at 1kHz prevents 100mVP-P input ripple from translating to >100µVP-P output noise-maintaining <0.5% EVM at 3.5GHz. |
Use Scenario: Supplying phase-locked loop core and voltage-controlled oscillator in satellite navigation receivers. IC Role / Device Role / Timing Role: Precision 5.0V reference source with ultra-low 1/f noise to minimize close-in phase jitter (<1° RMS @ 100Hz offset). Use Value: NP terminal tuning reduces integrated phase noise by 3–5dB compared to standard LDOs-enabling sub-2ns RMS jitter in 10MHz–1GHz synthesizers. |
| Low-Noise Image Sensors | High-Speed ADC/DAC Supplies |
|
Use Scenario: Biasing CMOS image sensor analog front-end (AFE) in medical endoscopes requiring <1 LSB noise floor at 14-bit resolution. IC Role / Device Role / Timing Role: Dedicated 5.0V LDO for sensor pixel array and column amplifier, isolated from digital switching noise. Use Value: 0.1µF ceramic output capacitor suffices for stability-avoiding tantalum ESR variability and enabling compact 0402 footprint placement adjacent to sensor die. |
Use Scenario: Powering 16-bit, 1MSPS SAR ADCs in portable test equipment where supply-induced code errors degrade measurement accuracy. IC Role / Device Role / Timing Role: Ultra-stable 5.0V rail for ADC reference buffer and analog input stage, rejecting digital supply coupling. Use Value: ±50mV output tolerance ensures <0.3 LSB error contribution-meeting ENOB >15.5 bits specification without calibration overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-noise LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AP2204-5.0TRG1 | Lower max current (150mA), higher dropout (250mV @ 100mA), no NP terminal-no adjustable PSRR tuning. | Suitable for lower-power sensor interfaces but not RF power stages or high-current AFEs. | Select when cost sensitivity outweighs PSRR/noise performance and load current stays below 150mA. |
| TLC7605CDR | Higher quiescent current (120µA), wider input range (2.7–16V), ±2% output tolerance-less precise than AP1152ADU50. | Better for industrial PLC I/O modules needing extended VIN range, less ideal for precision imaging or RF. | Choose when operating above 85°C ambient or requiring >14.5V input; avoid for <12-bit precision analog rails. |
Compared with AP2204-5.0TRG1 and TLC7605CDR, the AP1152ADU50 delivers superior PSRR (80dB vs. 65dB), tighter output accuracy (±1.5% vs. ±2%), and configurable noise filtering via NP-making it the optimal choice for RF, imaging, and high-resolution data acquisition where supply integrity directly impacts system-level SNR and jitter.
Availability
AP1152ADU50 is available at Aetrix Electronics and suitable for RF power supplies, PLL/VCO biasing, low-noise image sensor units, and high-speed ADC/DAC applications requiring stable component supply, consistent parametric performance, and long-term manufacturing continuity.
Supply support for AP1152ADU50 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global semiconductor manufacturer specializing in discrete, analog, and mixed-signal solutions, with emphasis on power management, signal integrity, and protection devices for industrial, automotive, and consumer markets.
The AP1152 series is designed as a high-PSRR, low-noise LDO family targeting noise-critical analog power domains-including RF transceivers, precision data converters, and high-speed imaging-where traditional regulators fail to meet stringent ripple and stability requirements.
FAQ
What is the maximum output current capability of the AP1152ADU50 under continuous operation?
The AP1152ADU50 delivers 300mA continuous output current at 25°C ambient with proper PCB thermal relief. At 85°C ambient, derating applies: maximum sustainable current drops to approximately 240mA due to thermal resistance (θJA = 138°C/W) and internal thermal shutdown threshold (~150°C junction). Full 300mA is guaranteed across –40°C to +85°C per datasheet Section 10.
Can the AP1152ADU50 operate stably with only a 0.1µF ceramic output capacitor?
Yes-the AP1152ADU50 is explicitly characterized for stable operation with a 0.1µF ceramic capacitor on the VOUT pin when VOUT ≥ 2.5V. This is confirmed in Section 1. General Description and Section 11.4, which states "Operation is stabilized by 0.1µF (VOUT ≥ 2.1V) the output side capacitor." For 5.0V output, 0.1µF X5R/X7R MLCC (e.g., 0402 or 0603) meets stability requirements without ESR dependency.
How does the NP (Noise Pass) terminal affect the AP1152ADU50's performance?
The NP terminal on the AP1152ADU50 connects to an internal noise-filtering node. Adding a capacitor (typically 1nF–10nF) between NP and GND improves low-frequency PSRR-up to 15dB enhancement below 10kHz-and reduces output voltage noise. However, larger NP capacitors slow VOUT rise/fall times during on/off transitions, as documented in Section 11.6 and Figure 17.
What is the recommended on/off control voltage threshold for the AP1152ADU50's VCONT pin?
The AP1152ADU50 VCONT pin has a defined high-active logic threshold: output enables when VCONT ≥ 1.8V and disables when VCONT ≤ 0.35V (Section 11.5, Table 4). An internal 500kΩ pull-down resistor ensures reliable OFF-state behavior when the pin is left floating or driven by open-drain logic. CMOS outputs (e.g., 3.3V or 5V GPIO) interface directly without level-shifting.
Does the AP1152ADU50 require an input capacitor, and if so, what value is recommended?
Yes-an input capacitor is required for transient suppression and stability, especially with high-impedance sources like batteries or long PCB traces. Section 13 specifies a recommended 1.0µF ceramic capacitor (X5R/X7R, 10V rating) placed adjacent to VIN and GND pins. This value minimizes line transients and ensures robust start-up behavior per Figure 19 and Section 11.4.
AP1152ADU50 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Asahi Kasei Microdevices/AKM
- Series:
- -
- Package/Case:
- SOT-89-5/6
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 14.5V
- Voltage - Output (Min/Fixed):
- 5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.44V @ 300mA
- Current - Output:
- 300mA
- Current - Quiescent (Iq):
- 100 µA
- Current - Supply (Max):
- 3.6 mA
- PSRR:
- 80dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Reverse Polarity, Short Circuit
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-89-5
AP1152ADU50 FAQ
1.How can I place an order for AP1152ADU50 through Aetrix?
Please submit a Request for Quotation (RFQ) for AP1152ADU50 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AP1152ADU50 reliable?
The price and inventory of AP1152ADU50 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AP1152ADU50 is usually 5 days.
3.What payment methods are accepted for AP1152ADU50?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AP1152ADU50 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AP1152ADU50?
AP1152ADU50 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AP1152ADU50 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AP1152ADU50?
For technical support, including AP1152ADU50 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AP1152ADU50 requirements.
6.How does Aetrix verify that AP1152ADU50 is sourced from the original manufacturer or authorized distributors?
All AP1152ADU50 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AP1152ADU50 meets industry standards.
7.What is the process for return or replacement of AP1152ADU50?
All AP1152ADU50 units undergo pre-shipment inspection (PSI). If there is an issue with AP1152ADU50, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AP1152ADU50 part is unused and in its original packaging.
Return procedure for AP1152ADU50:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AP1152ADU50 Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

