Diodes Incorporated AP3306S10-13

Overview

AP3306S10-13 from Diodes Incorporated is a highly integrated Active Clamp Flyback (ACF) PWM controller for offline AC-DC power supplies, featuring 22–125 kHz switching frequency range, 0.56 V current sense threshold, ±3% frequency dithering, built-in X-CAP discharge, and SO-10 (Type A1) package. It enables ultra-low standby power (<0.33 mA burst mode), ZVS operation, and wide-output-voltage support for USB-PD 3.0 PPS chargers.

For engineers reviewing the AP3306S10-13 datasheet, AP3306S10-13 pinout, AP3306S10-13 application, or AP3306S10-13 equivalent, key selection criteria include active clamp control logic, dual gate drivers (GDH/GDL) for high-side PMOS and low-side NMOS, VCCL LDO regulation (10–50 V input), HV startup capability (700 V max), and secondary-side OVP/UVP protection with DEM pin sampling.

Technical Context

The AP3306 implements a patented Smart Active Clamp Control Strategy combining valley switching and jittered ZVS to recycle leakage energy and minimize switching loss across universal input (90–264 VAC). Its dual-mode operation-valley-switching at low line/full load and ZVS-with-jitter at high line-ensures consistent efficiency and EMI compliance without external compensation.

It integrates a dedicated HV startup circuit with fault-aware charge current (ICHARGE-L/ICHARGE-H/ICHARGE-FAULT), a VCCH-to-VCCL LDO enabling 10–50 V VCCL operation, and a DEM pin that performs simultaneous functions: demagnetization detection, SOVP/SUVP sampling (with 1.8 µs delay), and OCP line compensation-enabling single-pin secondary-side monitoring.

Key Specifications

Pinout & Package

AP3306S10-13 is housed in a SO-10 (Type A1) surface-mount package with exposed thermal pad (JEDEC MS-012 variant), 1.75 mm max height, and matte tin annealed lead finish compliant with J-STD-020 Level 3 moisture sensitivity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar active clamp flyback controller applications.

Compared with NCP1566 and INN3377C, the AP3306S10-13 uniquely combines wide VCCL regulation (10–50 V), dual gate drivers, and X-CAP discharge-making it optimal for high-density, variable-output USB-PD chargers where standby power, board space, and secondary-side protection integration are critical.

Availability

AP3306S10-13 is available at Aetrix Electronics and suitable for smartphone quick chargers, notebook computer adapters, and open-frame switching power supplies requiring stable component supply, long-term lifecycle support, and RoHS-compliant manufacturing.

Supply support for AP3306S10-13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and ICs, specializing in power management, signal integrity, and protection solutions for consumer, industrial, and computing markets.

The AP3306 belongs to Diodes' Active Clamp Flyback Controller product line, engineered specifically for high-efficiency, high-power-density offline AC-DC converters targeting USB-PD, QC, and other programmable power supply standards.

FAQ

What is the purpose of the DEM pin in AP3306S10-13?

The DEM pin serves three concurrent functions: detecting transformer demagnetization timing to enable ZVS, sampling auxiliary winding voltage for secondary-side OVP (3.2 V threshold) and UVP (0.4 V threshold), and providing line-voltage-compensated current sense for accurate OCP across input range. It operates with a fixed 1.8 µs sample delay after GATE falling edge.

How does the HV pin support both startup and X-CAP discharge?

The HV pin senses AC line voltage for brown-in/out protection and provides startup current to VCCL until VST (15.8 V) is reached. When AC is removed, an internal 40 ms timer detects disconnection and activates a 1.7 mA discharge current through HV→GND for 40 ms, repeating until HV voltage falls below 10 V-eliminating need for external bleeder resistors.

Can AP3306S10-13 drive both high-side PMOS and low-side NMOS simultaneously?

Yes-GDH drives the gate of a high-side PMOS (source tied to VCCL) by pulling down to turn on and pulling up to VCCL to turn off; GDL drives a low-side NMOS (source tied to GND) with standard logic-level output. Both drivers operate with matched timing and support independent dead-time control via internal logic.

What protection features trigger automatic restart versus latched shutdown?

All protections-including BNO, FOCP, SOVP, SUVP, VOVP, OTP, and OCP-cause immediate shutdown and automatic restart once VCCL falls below UVLO (6.5 V). No latched modes exist; recovery is fully autonomous, relying on VCC decay/recharge cycle, ensuring robustness in intermittent fault conditions like line sags or transient shorts.