Diodes Incorporated AP3421BDNTR-G1

Overview

AP3421BDNTR-G1 from BCD Semiconductor is a dual-channel synchronous step-down DC-DC converter IC with integrated high- and low-side MOSFETs, delivering up to 1.0A per output at adjustable voltages (VO1: 1.8–3.6V; VO2: 1.0–3.6V), operating at a fixed 1.3MHz switching frequency with 180° phase shift between channels, and featuring Power-On Reset (POR), enable/synchronization (E/S), and thermal/over-current protection - used in multi-rail power systems for set-top boxes and hard disk drives.

For engineers reviewing the AP3421BDNTR-G1 datasheet, AP3421BDNTR-G1 pinout, AP3421BDNTR-G1 application, or AP3421BDNTR-G1 equivalent, key selection criteria include dual-output sequencing control, DFN-3×3-10 package thermal performance (θJA = 33°C/W), discharge-before-turn-on functionality (AP3421/A variant), pre-bias support (AP3421B variant), and external clock synchronization capability (1.5–3.0MHz lock-in range).

Technical Context

The AP3421BDNTR-G1 implements two independent current-mode synchronous buck regulators with internal compensation, each supporting resistor-programmable output voltage and soft-start with controlled power-up sequencing (VO1 precedes VO2). Its architecture integrates control logic, gate drivers, and power MOSFETs (RDS(on) upper: 260–300mΩ; lower: 160–260mΩ at VIN=3.3–5V), eliminating external rectifiers.

It features a dedicated open-drain POR pin monitoring FB1, FB2, and VMON with deglitched fault detection (10–40µs assert delay, 10–30ms release hold), plus pulse-skipping mode for light-load efficiency and E/S pin support for static enable/disable or external clock synchronization at half-frequency (e.g., 2.6MHz input → 1.3MHz operation).

Key Specifications

Pinout & Package

AP3421BDNTR-G1 is housed in a thermally enhanced DFN-3×3-10 package (3mm × 3mm, 0.75mm height) with exposed thermal pad (PGND-connected) for efficient heat dissipation in space-constrained applications.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output synchronous buck regulator applications.

Compared with TPS65261RHBR and RTQ2132BGQW, AP3421BDNTR-G1 offers optimal cost-performance balance for fixed-voltage, thermally constrained dual-rail applications - its DFN-3×3-10 footprint and 33°C/W θJA deliver superior power density without I²C overhead or excessive pin count.

Availability

AP3421BDNTR-G1 is available at Aetrix Electronics and suitable for set-top box power management, hard disk drive dual-rail supply, and industrial camera sensor bias applications requiring stable component supply, RoHS-compliant green packaging (G1 suffix), and long-term industrial temperature support (-40°C to +85°C).

Supply support for AP3421BDNTR-G1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

BCD Semiconductor Manufacturing Limited is a Shanghai-based fabless analog IC designer specializing in high-efficiency power management, LED drivers, and mixed-signal solutions for consumer, industrial, and computing markets.

The AP3421 series belongs to BCD's dual-output synchronous buck regulator product line, engineered specifically for cost-sensitive, space-constrained multi-rail systems requiring precise sequencing, robust fault protection, and minimal external components.

FAQ

What is the function of the VMON pin on AP3421BDNTR-G1?

The VMON pin monitors an external voltage rail (e.g., input supply or auxiliary rail) and feeds that signal into the internal POR comparator. If VMON falls below 0.97–1.03V, the POR pin pulls low to signal a system-level undervoltage condition. This provides supervision beyond the two regulated outputs, enabling comprehensive power integrity checking in multi-supply systems.

Does AP3421BDNTR-G1 support pre-bias start-up?

No - AP3421BDNTR-G1 is the base variant and does not include pre-bias start-up functionality. That feature is exclusive to the AP3421B version (e.g., AP3421BDNTR-G1 is *not* AP3421B). Attempting to start into a pre-charged output may cause reverse current flow; use AP3421BDNTR-G1 only with discharged outputs or add external diode protection.

How does the E/S pin enable external clock synchronization?

When a square-wave clock signal (1.5–3.0MHz) is applied to the E/S pin, the internal oscillators lock to half that frequency - e.g., a 2.6MHz input yields synchronized 1.3MHz switching on both SW1 and SW2. The E/S pin must be driven with clean CMOS-level signals; AC coupling is not supported, and duty cycle should be 40–60% for reliable locking.

What thermal derating applies to AP3421BDNTR-G1 at 85°C ambient?

With θJA = 33°C/W and TJ(max) = 150°C, the maximum allowable power dissipation at TA = 85°C is (150 − 85) / 33 ≈ 1.97W. At full 1A per channel and typical RDS(on), total conduction loss is ~0.35W - well within limit. However, PCB copper area and airflow must maintain junction temperature ≤150°C; minimum 100mm² 2-oz copper under thermal pad is recommended.