Diodes Incorporated AP61302QZ6-EVM

Overview

AP61302QZ6-EVM from Diodes Incorporated is an evaluation board for the AP61302Q 3A synchronous buck converter, supporting 2.4V–5.5V input and delivering up to 3A at programmable output voltages from 0.6V to VIN. It integrates 70mΩ high-side and 50mΩ low-side MOSFETs in SOT563, uses constant-on-time (COT) control for fast transient response, and operates at 2.2MHz with ultralow 19µA quiescent current in PFM mode. Designed for point-of-load evaluation in consumer and embedded power systems.

For engineers reviewing the AP61302QZ6-EVM datasheet, AP61302QZ6-EVM pinout, AP61302QZ6-EVM application, or AP61302QZ6-EVM equivalent, this page provides verified board-level specifications, test-point access details, VOUT configuration guidance via R1/R2 divider, efficiency curves across load conditions, and direct support for 1.8V default output validation under 3A load.

Technical Context

The AP61302QZ6-EVM implements a fixed-layout reference design for the AP61302Q IC, featuring a 1.0µH shielded SMD inductor (Würth 744316100), dual 22µF X5R ceramic input/output capacitors (Taiyo Yuden EMK212ABJ106KD-T), and precision 1% resistor network (R1=200kΩ, R2=100kΩ) setting VOUT=1.8V per the 0.6V ±2% internal reference.

It supports dual modulation modes-PFM for light-load efficiency and forced PWM via EN pin voltage threshold (VIN–VEN > 200mV)-and includes full protection coverage: UVLO, VIN OVP, peak/valley current limiting, and thermal shutdown, all directly inherited from the AP61302Q die.

Key Specifications

Availability

AP61302QZ6-EVM is available at Aetrix Electronics and suitable for FPGA power sequencing, wireless router PoL regulation, and network camera DC-DC conversion requiring stable component supply and rapid prototyping capability.

Supply support for AP61302QZ6-EVM includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, headquartered in Plano, Texas, with design and manufacturing operations across Asia and the Americas.

The AP61302Q product line targets high-efficiency, space-constrained point-of-load applications in consumer, industrial, and networking equipment, emphasizing minimal external component count and fast transient response via COT architecture.

FAQ

What is the default output voltage and how is it configured?

The AP61302QZ6-EVM is factory-configured for 1.8V output using a 200kΩ (R1) and 100kΩ (R2) resistor divider tied to the FB pin. This leverages the device's 0.6V ±2% internal reference per the equation VOUT = 0.6V × (1 + R1/R2). The resistors are 1% tolerance 0805 chips placed per the schematic on page 5 of the EVM user guide.

How do I enable or disable the converter on this board?

Enable/disable is controlled via a jumper on the EN signal: placing the jumper at "H" connects EN to VIN, enabling the converter; placing it at "L" grounds EN, disabling the device and halting switching activity. This matches the AP61302Q's EN pin logic-active-high with 200mV hysteresis between PFM and forced PWM modes.

Can I change the output voltage, and what components must be modified?

Yes-output voltage is fully adjustable via the R1/R2 feedback divider. To change VOUT, replace R1 and/or R2 with values satisfying VOUT = 0.6V × (1 + R1/R2); Table 1 in the datasheet provides standard resistor pairs for common voltages. R1 and R2 are 0805 1% resistors located near U1 and accessible for rework.

What test points are provided for performance validation?

The board includes dedicated test points for VIN, GND, VOUT, SW, EN, and PG (Power Good). SW allows direct oscilloscope measurement of switching waveform and frequency; VOUT/GND enables ripple and load-regulation verification; PG confirms proper startup sequencing. All test points are labeled silkscreen and match the schematic in Figure 2.