Diodes Incorporated AP7165-SPG-13

Overview

AP7165-SPG-13 from Diodes Incorporated is a 600mA adjustable-output ultra-low dropout linear regulator with Power-OK (POK) monitoring, EN control, ±2.5% total output accuracy over line/load/temperature, 300mV dropout at 500mA, and 125µA typical quiescent current. It operates from 2.2V–5.5V input and delivers 0.8V–5.0V output, used in FPGA/DSP core power, portable audio, and battery-powered systems.

For engineers reviewing the AP7165-SPG-13 datasheet, AP7165-SPG-13 pinout, AP7165-SPG-13 application, or AP7165-SPG-13 equivalent, key selection factors include POK threshold hysteresis (4% V_REF), SO-8EP thermal resistance (27°C/W), open-drain POK logic compatibility, and stability with ≥4.7µF ceramic output capacitors without ESR requirements.

Technical Context

The AP7165 integrates a PMOS pass transistor, bandgap reference (0.8V), error amplifier, and current-limit/thermal-shutdown circuitry. Its POK output asserts high when FB voltage reaches 87–97% of V_REF, with 150µs deglitch timing and 100–200mV low-level sink capability under 2mA load.

Enable logic requires VIH ≥1.4V and VIL ≤0.4V; shutdown draws ≤0.01µA. The regulator maintains regulation down to zero load and achieves 60dB PSRR at 1kHz while delivering fast transient response via internal compensation optimized for ≥4.7µF ceramic output capacitance.

Key Specifications

Pinout & Package

AP7165-SPG-13 uses the SO-8EP (SOP-8L-EP) package with exposed thermal pad. Pin assignments are validated per Diodes DS31270 Rev. 7–2: IN (pins 1,2), POK (pin 3), EN (pin 4), GND (pin 5), FB (pin 6), OUT (pins 7,8). NC pins absent in SO-8EP variant.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar adjustable LDO regulator applications.

Compared with XC6210B182MR-G and MIC5205-3.3YM5, AP7165-SPG-13 uniquely combines 600mA adjustability, integrated POK for sequencing, and ultra-low dropout-enabling single-LDO solutions for FPGA core/I/O and portable audio where voltage flexibility and system coordination are essential.

Availability

AP7165-SPG-13 is available at Aetrix Electronics and suitable for FPGA power delivery, portable audio subsystems, and USB-C interface regulation requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for AP7165-SPG-13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in high-reliability power management, signal integrity, and protection solutions for industrial, computing, and consumer markets.

The AP7165 belongs to Diodes' precision LDO family designed for noise-sensitive, battery-constrained applications demanding tight regulation, low IQ, and integrated power sequencing-particularly in portable computing and audio endpoints.

FAQ

What is the minimum output capacitor required for stability?

The AP7165-SPG-13 is stable with any output capacitor ≥4.7µF, including ceramic, tantalum, or electrolytic types-no ESR minimum is required. This eliminates capacitor selection risk and simplifies design for space-constrained layouts where low-ESR ceramics are preferred.

How does the POK pin behave during startup and fault conditions?

POK asserts high after start-up time (170µs typical) when FB voltage exceeds 87% of 0.8V reference, with 4% hysteresis to prevent chatter. During undervoltage or thermal shutdown, POK goes open-drain low; it remains inactive (high-impedance) if left floating or pulled up beyond 5.5V.

Can the AP7165-SPG-13 be used without the EN pin connected?

Yes-the EN pin may be tied directly to the IN rail to maintain permanent enable. However, doing so forfeits dynamic power control; for battery-powered systems, connecting EN to a processor GPIO enables software-controlled sleep/wake cycles with <0.01µA shutdown current.

What thermal considerations apply to the SO-8EP package in high-power operation?

With θJA = 27°C/W, the SO-8EP package dissipates up to 4.0W at 25°C ambient. To avoid thermal shutdown at 85°C ambient, power dissipation must stay below ~2.2W-requiring VIN–VOUT < 3.7V at 600mA. Use of the exposed pad with ≥1.5"² copper area is mandatory for rated performance.