Diodes Incorporated AP7173-SPG-13

Overview

AP7173-SPG-13 from Diodes Incorporated is a 1.5A low-dropout linear regulator with programmable soft-start, power-good (PG) open-drain output, and bias-supplied NMOS pass FET architecture. It operates from 1.0V to 5.5V input, delivers 0.8V–3.3V adjustable output with ±2% accuracy over line/load/temperature, and achieves 165mV typical dropout at 1.5A with VVCC = 5V. Used in FPGA core voltage sequencing where precise ramp control and supply monitoring are required.

For engineers reviewing the AP7173-SPG-13 datasheet, AP7173-SPG-13 pinout, AP7173-SPG-13 application, or AP7173-SPG-13 equivalent, this page provides verified package mapping (SO-8EP), confirmed soft-start capacitor timing relationships, PG threshold hysteresis (3% VOUT), bias voltage dependency (VVCC ≥ VIN), and thermal shutdown behavior (150°C trip / 130°C reset).

Technical Context

The AP7173 employs an NMOS pass transistor driven by a separate VVCC bias rail (2.7V–5.5V), enabling ultra-low dropout while maintaining stable regulation at VIN as low as 1.0V. Its feedback loop references a precision 0.8V internal bandgap, supporting output programming via external resistor divider with ≤5kΩ R2 for optimal accuracy.

Soft-start is implemented as a voltage-ramp tracker: external capacitor CSS charges at 440nA, yielding monotonic VOUT rise per tSS = 0.8 × CSS / 4.4×10⁻⁷. The open-drain PG pin asserts low when VOUT falls below 85–94% of nominal, with 3% hysteresis and 1mA sink capability at ≤0.3V.

Key Specifications

Pinout & Package

AP7173-SPG-13 is packaged in SO-8EP (exposed pad), with pins arranged in standard 8-lead SOP outline and thermal pad soldered to PCB ground plane for enhanced heat dissipation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TPS7A8300RGRT and ADM7172ACPZ-R7, AP7173-SPG-13 uniquely supports 1.0V minimum VIN via dedicated VVCC bias, fully programmable soft-start timing, and 0.8V–3.3V output adjustability-making it the only option for low-voltage FPGA core sequencing with strict ramp control and supply independence.

Availability

AP7173-SPG-13 is available at Aetrix Electronics and suitable for FPGA power sequencing, DSP I/O regulation, server memory subsystems, and industrial PLC CPU core supplies requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for AP7173-SPG-13 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in power management, signal integrity, and protection solutions for industrial, computing, and communications markets.

The AP7173 belongs to Diodes' high-performance LDO family designed specifically for low-VIN, high-accuracy, multi-rail power sequencing in FPGA, ASIC, and DSP systems where bias-supplied NMOS architecture enables superior dropout and transient response.

FAQ

What is the minimum input voltage required for AP7173-SPG-13 to regulate 1.2V output?

The AP7173-SPG-13 supports VIN as low as 1.0V, but achieving 1.2V output requires VVCC ≥ VIN and sufficient headroom for dropout. With VVCC = 5V, dropout is 165mV at 1.5A, so VIN ≥ 1.365V is required. If VVCC = VIN, minimum VIN rises to 2.9V due to higher dropout (1.7V typical). Always maintain VVCC ≥ VIN per datasheet Section 10.

Can the PG pin be pulled up to a voltage higher than VIN?

Yes-the PG pin is rated for up to 6V absolute maximum and may be pulled up to any rail ≤5.5V, including VOUT, VIN, or a separate 3.3V/5V supply. This enables flexible sequencing: e.g., pulling PG to a 3.3V rail allows direct interfacing with 3.3V FPGA configuration logic even when VOUT = 1.0V.

How does the soft-start capacitor value affect startup behavior?

Soft-start time tSS (seconds) = 0.8 × CSS (farads) / 4.4×10⁻⁷. For example, 5.6nF yields ~10ms ramp; 270pF yields ~0.5ms. Larger CSS extends ramp duration linearly, reducing inrush into bulk capacitors and preventing brownout on shared input rails-critical for multi-regulator systems.

Is thermal pad connection mandatory for SO-8EP package operation?

Yes-the exposed thermal pad in SO-8EP is electrically connected to GND and serves as the primary heat conduction path. Per datasheet Figure 27 and Thermal Characteristics table, θJA = 23°C/W assumes full pad soldering to ≥1in² copper area. Omitting pad connection degrades thermal performance by >50%, risking thermal shutdown at ≤1.0A load.