Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Diodes Incorporated AP7342D-3318FS6-7

Name: AP7342D-3318FS6-7
Brand: Diodes Incorporated
SKU: AP7342D-3318FS6-7
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: AP7342D-3318FS6-7

Manufacturer:: Diodes Incorporated

Category:: Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Package:: 6-XFDFN Exposed Pad

Datasheet:: AP7342D-3318FS6-7.pdf

Description:: IC REG LIN 1.8V/3.3V X2DFN1212-6

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,865

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

AP7342D-3318FS6-7 from Diodes Incorporated is a dual-channel, CMOS-based low-dropout linear regulator with independent enable control per channel, delivering fixed 3.3V and 1.8V outputs at up to 150mA each. It features ±1% output voltage accuracy over temperature, 75dB PSRR at 1kHz, 60µV_rms output noise (10Hz–100kHz), and ultra-low 35µA quiescent current in single-channel active mode. Designed for RF supply rails and portable media subsystems, it operates from 1.7V to 5.25V input and uses the X2-DFN1212-6 package for space-constrained PCB layouts.

For engineers reviewing the AP7342D-3318FS6-7 datasheet, AP7342D-3318FS6-7 pinout, AP7342D-3318FS6-7 application, or AP7342D-3318FS6-7 equivalent, key selection criteria include dual-rail sequencing capability, low-noise performance for analog/RF stages, thermal dissipation limits in DFN1212, and compatibility with 0.47µF ceramic output capacitors.

Technical Context

The AP7342D-3318FS6-7 integrates two independent LDO regulators sharing a common input and ground, each with dedicated EN1/EN2 control pins enabling asynchronous power-up/down of 3.3V and 1.8V rails. Its CMOS pass device architecture delivers low dropout (0.22V typical at 150mA for 3.3V output) and eliminates body diode reverse conduction-critical for bidirectional isolation in multi-rail systems.

Each channel includes internal current limiting (~55mA foldback short-circuit protection), thermal shutdown, and built-in discharge circuitry (denoted by "D" suffix) that actively pulls VOUT to GND when disabled-preventing floating bias in downstream logic. The device requires no external compensation and remains stable with 0.47µF ceramic output capacitors.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltages	3.3V (Channel 1) and 1.8V (Channel 2), fixed via internal resistor network - eliminates external feedback components and simplifies layout.
Output Accuracy	±1% at +25°C, ±1.5% over −40°C to +85°C - ensures reliable logic-level compliance for 3.3V I/O and 1.8V core supplies.
PSRR	75dB at 1kHz - suppresses switching noise from upstream DC/DC converters feeding noisy battery or PMIC rails.
Output Noise	60µV_rms (10Hz–100kHz) - meets low-noise requirements for RF transceivers, camera ISPs, and precision ADC reference supplies.
Quiescent Current	35µA (one channel active, other disabled) - extends battery life in always-on sensor or standby subsystems.
Dropout Voltage	0.22V (max) at 150mA for 3.3V output - enables operation down to 3.52V input, supporting single-cell Li-ion with aging margin.
Enable Thresholds	V_EN(H) ≥ 1.3V, V_EN(L) ≤ 0.5V - compatible with 1.8V/3.3V GPIO without level-shifting.

Pinout & Package

X2-DFN1212-6 package: 1.2mm × 1.2mm, 0.4mm height, 0.4mm pitch, thermally enhanced with exposed pad (not electrically connected to GND by default).

Pin/Terminal	Circuit Role	Design Meaning
1	VOUT1	3.3V regulated output - connects directly to 3.3V domain loads (e.g., USB PHY, SDIO interface).
2	VOUT2	1.8V regulated output - powers 1.8V logic cores (e.g., FPGA I/O banks, LPDDR2/3 VDDQ).
3	GND	Analog/digital ground reference - must be low-impedance connection to PCB ground plane.
4	EN2	Active-high enable for Channel 2 (1.8V) - tie high to VIN or controlled by system PMIC for sequenced power-up.
5	VIN	Common input (1.7V–5.25V) - requires 0.47µF ceramic capacitor placed adjacent to pin.
6	EN1	Active-high enable for Channel 1 (3.3V) - supports independent control of 3.3V rail for peripheral isolation.

Key Features

Feature	Design Value
Dual independent enable inputs	EN1 and EN2 allow asynchronous start-up/shutdown of 3.3V and 1.8V rails - essential for power sequencing in SoC-based designs.
Built-in output discharge	Active pull-down on VOUT1/VOUT2 when respective EN pin is low - prevents residual voltage hold-up that could cause latch-up in downstream logic.
Stable with 0.47µF ceramic COUT	Eliminates need for bulk electrolytic capacitors - reduces board area and improves reliability in portable devices.
Low 60µV_rms noise	Enables direct use in noise-sensitive analog signal chains (e.g., audio codecs, RF front-end biasing) without additional filtering.
−40°C to +85°C operation	Qualified for industrial and extended commercial environments - suitable for automotive infotainment and ruggedized handhelds.

Applications

Smartphone Baseband Power

RF Transceiver Bias

Use Scenario: Dual-rail power for LTE/Wi-Fi baseband processor requiring isolated 3.3V I/O and 1.8V core domains.

IC Role / Device Role / Timing Role: Primary LDO supplying both voltage domains with independent enable control for power-state transitions.

Use Value: Enables precise sequencing (1.8V before 3.3V) and fast rail disable during sleep modes, reducing system leakage by >90%.

Use Scenario: Clean bias supply for GaAs pHEMT driver amplifiers and LNA stages in 5G mmWave front-ends.

IC Role / Device Role / Timing Role: Low-noise post-regulator cleaning switched-mode supply ripple before RF signal path.

Use Value: 60µV_rms noise and 75dB PSRR maintain EVM < 2.5% at 28GHz, avoiding costly ferrite-bead filtering.

Camera Image Signal Processor

Portable Media Player Audio Core

Use Scenario: Dedicated 1.8V supply for CIS image sensor digital interface and 3.3V for analog pixel array biasing.

IC Role / Device Role / Timing Role: Dual-output LDO decoupling digital and analog domains to prevent crosstalk-induced fixed-pattern noise.

Use Value: Independent EN control allows sensor reset timing alignment; low dropout preserves headroom under battery droop.

Use Scenario: Powering DAC, headphone amplifier, and codec digital core in battery-powered MP3 players.

IC Role / Device Role / Timing Role: Ultra-low-quiescent LDO delivering clean 3.3V (codec I/O) and 1.8V (DAC reference) rails.

Use Value: 35µA single-rail IQ extends playback time by 12+ hours on 500mAh battery; 60µV_rms noise ensures THD < −95dB.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-output LDO applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AP7345D-3318FS6-7	Successor device with improved PSRR (80dB @ 1kHz), lower noise (45µV_rms), and AEC-Q100 Grade 2 qualification.	Required for new automotive designs; supports wider input range (1.4V–5.5V) and higher ambient temp (−40°C to +105°C).	Select when designing for automotive or next-gen portable systems needing tighter noise/PSRR specs and extended temp support.
TPL7407LPGEDR	Single-channel 150mA LDO (3.3V only), no dual output or discharge function; 55dB PSRR, 120µV_rms noise.	Suitable only for 3.3V-only applications; lacks 1.8V rail and independent enable control.	Use only if second rail is generated elsewhere (e.g., separate 1.8V LDO or DC/DC); not a drop-in replacement.

Compared with AP7342D-3318FS6-7, the AP7345D offers measurable improvements in noise and PSRR for RF/analog systems, while the TPL7407LPGEDR provides cost reduction in single-rail designs but sacrifices sequencing flexibility and noise performance.

Availability

AP7342D-3318FS6-7 is available at Aetrix Electronics and suitable for smartphone baseband power, RF transceiver bias, and camera ISP applications requiring stable component supply across industrial temperature ranges and long production lifecycles.

Supply support for AP7342D-3318FS6-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Diodes Incorporated is a global manufacturer of discrete semiconductors and analog ICs, specializing in power management, signal integrity, and protection solutions for consumer, industrial, and automotive markets.

The AP7342 belongs to Diodes' high-PSRR, low-noise LDO family targeting portable and RF-sensitive applications where clean, sequenced dual-rail power is critical - not general-purpose regulation.

FAQ

What is the thermal pad on the X2-DFN1212-6 package used for?

The exposed thermal pad on the AP7342D-3318FS6-7's X2-DFN1212-6 package is intended for thermal dissipation, not electrical grounding. Diodes recommends connecting it to a large copper pour tied to GND for optimal heat transfer, but it must not serve as the sole GND connection - the dedicated Pin 3 (GND) remains the primary ground reference for stability and noise control.

Can EN1 and EN2 be tied together for simultaneous control?

Yes, EN1 and EN2 may be connected to a common enable signal for synchronized 3.3V/1.8V rail activation. However, doing so forfeits independent sequencing capability. When tied, ensure the driving source meets both pins' input leakage (<±1.0µA) and voltage thresholds (V_EN(H) ≥ 1.3V, V_EN(L) ≤ 0.5V) simultaneously under all operating conditions.

Is the 60µV_rms output noise measured with load?

Yes, the 60µV_rms output noise specification is measured at I_OUT = 30mA, across 10Hz–100kHz bandwidth, with 0.47µF ceramic output capacitors. This reflects real-world loaded conditions - unlike no-load noise measurements, which can be misleading for battery-powered systems with dynamic current draw.

Why does the datasheet state "NOT RECOMMENDED FOR NEW DESIGNS"?

Diodes has designated AP7342D-3318FS6-7 as legacy due to the release of the enhanced AP7345D series, which offers superior PSRR (80dB), lower noise (45µV_rms), AEC-Q100 qualification, and extended input range. Existing designs may continue using AP7342D, but new projects should adopt AP7345D for improved performance and long-term supply assurance.

AP7342D-3318FS6-7 Specifications

Product attributes: Attribute value

Manufacturer:: Diodes Incorporated

Series:: -

Package/Case:: 6-XFDFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Output Configuration:: Positive

Output Type:: Fixed

Number of Regulators:: 2

Voltage - Input (Max):: 5.25V

Voltage - Output (Min/Fixed):: 1.8V, 3.3V

Voltage - Output (Max):: -

Voltage Dropout (Max):: 0.39V @ 150mA, 0.29V @ 150mA

Current - Output:: 150mA, 150mA

Current - Quiescent (Iq):: 100 µA

Current - Supply (Max):: -

PSRR:: 75dB (1kHz)

Control Features:: Enable

Protection Features:: Over Current

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: X2-DFN1212-6

AP7342D-3318FS6-7 FAQ

1.How can I place an order for AP7342D-3318FS6-7 through Aetrix?

Please submit a Request for Quotation (RFQ) for AP7342D-3318FS6-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AP7342D-3318FS6-7 reliable?

The price and inventory of AP7342D-3318FS6-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AP7342D-3318FS6-7 is usually 5 days.

3.What payment methods are accepted for AP7342D-3318FS6-7?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AP7342D-3318FS6-7 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AP7342D-3318FS6-7?

AP7342D-3318FS6-7 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AP7342D-3318FS6-7 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AP7342D-3318FS6-7?

For technical support, including AP7342D-3318FS6-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AP7342D-3318FS6-7 requirements.

6.How does Aetrix verify that AP7342D-3318FS6-7 is sourced from the original manufacturer or authorized distributors?

All AP7342D-3318FS6-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AP7342D-3318FS6-7 meets industry standards.

7.What is the process for return or replacement of AP7342D-3318FS6-7?

All AP7342D-3318FS6-7 units undergo pre-shipment inspection (PSI). If there is an issue with AP7342D-3318FS6-7, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AP7342D-3318FS6-7 part is unused and in its original packaging.

Return procedure for AP7342D-3318FS6-7:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…