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Microchip Technology AT17C002-10JI
- Part No.:
- AT17C002-10JI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 20-LCC (J-Lead)
- Datasheet:
-
AT17C002-10JI.pdf
- Description:
- IC SRL CONFIG EEPROM 2M 20PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,895
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Product details
Overview
AT17C002-10JI from Microchip Technology (formerly Atmel) is a 2-Mbit FPGA configuration EEPROM designed to store and serially load bitstream programs into SRAM-based FPGAs. It operates at 5V ±10% over -40°C to +85°C, features in-system programmability via 2-wire bus, supports cascading for multi-FPGA systems, and includes programmable reset polarity and system-friendly READY pin for power-up sequencing in industrial embedded control applications.
For engineers reviewing the AT17C002-10JI datasheet, AT17C002-10JI pinout, AT17C002-10JI application, or AT17C002-10JI equivalent, this device serves as a drop-in replacement for legacy Xilinx XC17PROMs and Atmel AT17C/LV020, with verified compatibility across Xilinx Virtex™, Spartan®, XC4000™, Altera FLEX®/APEX™, Lucent ORCA®, and Atmel AT40K/AT94K families.
Technical Context
The AT17C002-10JI implements a serial-access EEPROM architecture optimized for FPGA master serial mode, where CLK from the FPGA drives internal address/bit counters and DATA outputs configuration bits directly to FPGA DIN. Its RESET/OE pin combines active-low reset and active-high output enable, with polarity programmable via EEPROM bytes - enabling direct interface without external logic.
It supports two operational modes: FPGA loading mode (SER_EN = High) and 2-wire ISP mode (SER_EN = Low). In loading mode, CE and RESET/OE jointly control data output tri-state and counter reset; CEO provides daisy-chain enable signaling, while READY delivers open-collector power-good indication with 4.7 kΩ pull-up recommendation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2,097,152 × 1-bit (2 Mbit) nonvolatile EEPROM storage for full FPGA configuration bitstreams |
| Supply Voltage | 5V ±10% - supports industrial temperature range (-40°C to +85°C) without derating |
| Max Clock Frequency | 15 MHz - enables fast configuration loading compatible with Xilinx XC4000/Virtex and Altera FLEX timing budgets |
| Standby Current | <0.75 mA - low-power shutdown when CE is high, critical for energy-constrained industrial systems |
| Output Drive | Open-collector DATA and READY pins - allows wired-OR connection in multi-device configurations |
| Reset Polarity | Programmable via EEPROM bytes - eliminates hardware redesign when migrating between RESET-active-Low and OE-active-High FPGA platforms |
| Cascade Support | CEO output drives CE of next device - enables seamless expansion beyond 2 Mbit using multiple AT17C002-10JI units |
Pinout & Package
AT17C002-10JI is packaged in an 8-lead Leadless Array Package (LAP), 6 mm × 6 mm × 1 mm body, pin-compatible with standard 8-lead SOIC/VOIC footprints. This compact surface-mount package supports high-density PCB layouts and reflow soldering per JEDEC J-STD-020.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 DATA | I/O (open-collector) | Bi-directional configuration data line: outputs bitstream to FPGA DIN during loading; accepts programming data during ISP |
| 2 CLK | Input | FPGA CCLK-synchronized clock input that increments internal address and bit counters for sequential readout |
| 3 RESET/OE | Input | Combined reset (active Low) and output enable (active High); polarity programmable to match FPGA INIT or CON/DONE signal behavior |
| 4 CE | Input | Chip Enable (active Low): enables data output and counter increment only when OE is high; forces standby mode when high |
| 5 GND | Power | Ground reference; requires 0.2 µF decoupling capacitor adjacent to VCC pin for stable operation |
| 6 CEO(A2) | Output / Input | Chip Enable Output (active Low) for daisy-chaining; A2 is device-select input during ISP with internal pulldown |
| 7 SER_EN | Input | Serial Enable: must be tied to VCC for FPGA loading; pulled low to enter 2-wire ISP programming mode |
| 8 VCC | Power | +5V supply pin; supports 5V ±10% tolerance across industrial temperature range |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field updates of FPGA configuration without removing the device - reduces maintenance downtime in deployed industrial controllers |
| Cascadable CEO output | Allows up to four AT17C002-10JI devices to be chained for 8-Mbit total capacity - supports large FPGA arrays like Virtex-E or Stratix without external logic |
| Programmable reset polarity | Four EEPROM bytes configure RESET/OE behavior - eliminates board-level jumper changes when porting designs between Xilinx (RESET-Low) and Altera (OE-High) platforms |
| System-friendly READY pin | Open-collector output driven Low during power-on reset and released after VCC stabilization - synchronizes FPGA configuration start with valid supply rail |
| Low-power standby mode | Consumes <0.75 mA when CE is high - extends battery life in portable test equipment and reduces thermal load in enclosed enclosures |
Applications
| Industrial PLC Configuration | Xilinx Virtex Bitstream Storage |
|---|---|
|
Use Scenario: Storing and loading configuration bitstreams for Xilinx Virtex FPGAs used in real-time motion control modules within factory automation PLCs. IC Role / Device Role / Timing Role: Serial configuration EEPROM providing master-mode bitstream delivery synchronized to FPGA CCLK, with READY pin ensuring configuration begins only after stable 5V rail. Use Value: Eliminates need for external microcontroller or CPLD to manage configuration, reducing BOM count and firmware complexity in safety-critical control systems. |
Use Scenario: Replacing obsolete XC17V020 PROMs in legacy Xilinx Virtex-5-based communications baseband processing cards. IC Role / Device Role / Timing Role: Pin-compatible, functionally equivalent configuration memory supporting identical AC timing (15 MHz max clock, 50 ns data delays) and DC electrical specs. Use Value: Enables drop-in replacement without PCB revision, preserving qualification status and accelerating time-to-market for field upgrades. |
| Altera FLEX-Based Test Equipment | Multi-FPGA Aerospace Avionics |
|
Use Scenario: Configuring Altera FLEX10K20 FPGAs in automated test equipment requiring reliable, repeatable startup after power cycling. IC Role / Device Role / Timing Role: Provides deterministic configuration sequence via RESET/OE-controlled counter reset and CE-gated data output, meeting MIL-STD-810G power-cycle robustness requirements. Use Value: Guarantees consistent FPGA state on every power-up - critical for calibration accuracy and repeatability in metrology-grade instruments. |
Use Scenario: Cascading three AT17C002-10JI devices to configure a triple-redundant FPGA array in radiation-tolerant avionics subsystems. IC Role / Device Role / Timing Role: CEO-to-CE daisy-chain enables synchronized, fault-isolated configuration of independent FPGA channels with automatic handoff signaling. Use Value: Supports fail-operational architecture by allowing partial reconfiguration without disrupting active channels - essential for flight-critical functions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV002-10JI | 3.3V operation (3.0–3.6V), lower active current (5 mA), reduced max clock (10 MHz industrial) | Required for 3.3V FPGA systems (e.g., Xilinx Spartan-3); not suitable for 5V-only legacy boards | Select AT17LV002-10JI only when target FPGA uses 3.3V I/O banks and timing margins accommodate 10 MHz clock limit. |
| XCF02SVO20C | Xilinx proprietary 2-Mbit PROM; 3.3V-only, no SER_EN or programmable reset; fixed RESET-Low polarity | Designed exclusively for Xilinx FPGAs; lacks cross-vendor compatibility and ISP flexibility of AT17C002-10JI | Choose XCF02SVO20C only in new Xilinx-only designs where vendor lock-in is acceptable and field reprogramming is unnecessary. |
Compared with AT17LV002-10JI and XCF02SVO20C, the AT17C002-10JI uniquely supports 5V industrial systems, programmable reset polarity, and universal ISP - making it the only option for maintaining legacy 5V FPGA platforms while enabling future field updates.
Availability
AT17C002-10JI is available at Aetrix Electronics and suitable for industrial PLCs, FPGA-based communications infrastructure, aerospace avionics, and test equipment requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for AT17C002-10JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and continues to manufacture, support, and qualify legacy Atmel FPGA configuration devices under its broad analog and mixed-signal portfolio.
The AT17 Series was originally developed by Atmel to provide cost-effective, pin-compatible, and field-programmable alternatives to one-time-programmable PROMs for SRAM-based FPGAs across industrial, communications, and defense applications.
FAQ
What is the operating voltage range for AT17C002-10JI?
The AT17C002-10JI operates at 5V ±10%, meaning its valid supply range is 4.5V to 5.5V. This specification is guaranteed across the full industrial temperature range of -40°C to +85°C, as confirmed in the Absolute Maximum Ratings and Operating Conditions tables of the official datasheet (Rev. 2281D–12/01). The device draws less than 0.75 mA in standby mode at this voltage.
Does AT17C002-10JI support in-system programming (ISP)?
Yes, AT17C002-10JI supports in-system programming via its 2-wire serial interface. This is enabled by pulling the SER_EN pin low, which activates the ISP mode. Programming occurs at the nominal VCC supply voltage (5V), with all required programming voltages generated internally - no external high-voltage supply is needed. The AT17C002-10JI can be programmed using industry-standard programmers or Atmel's ATDH2225 ISP Cable.
How does the READY pin function on AT17C002-10JI?
The READY pin on AT17C002-10JI is an open-collector output driven Low during power-on reset and released (tri-stated) once VCC reaches a stable level. It serves as a system power-good indicator, allowing the FPGA to delay configuration start until supply rails are valid. A 4.7 kΩ pull-up resistor is recommended on this pin, as specified in the datasheet's "Pin Configurations" section and Example Circuits (Figures 1–4).
Is AT17C002-10JI pin-compatible with older Atmel configuration PROMs?
Yes, AT17C002-10JI is explicitly documented as a replacement for AT17C/LV020 and a drop-in alternative to Xilinx XC17PROMs. Its 8-lead LAP package (8CN4) maintains pin compatibility with 8-lead SOIC/VOIC footprints, and its pin functions - including DATA, CLK, RESET/OE, CE, CEO, SER_EN, READY, and VCC - match the signal mapping required by Xilinx, Altera, Lucent, and Atmel FPGA families per the "Pin Configurations" and "Example Circuits" sections of the datasheet.
Can multiple AT17C002-10JI devices be cascaded for larger FPGA configurations?
Yes, AT17C002-10JI supports cascading via its CEO (Chip Enable Output) pin, which goes active-Low when the internal address counter reaches its maximum value. This CEO signal connects directly to the CE input of the next AT17C002-10JI in the chain, enabling automatic handoff and continuous bitstream delivery. The datasheet confirms this capability in the "Cascading Serial Configuration EEPROMs" section and provides timing parameters (TOCK, TOCE) specific to cascaded operation.
AT17C002-10JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 20-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 2Mb
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-PLCC (9x9)
AT17C002-10JI FAQ
1.How can I place an order for AT17C002-10JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C002-10JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C002-10JI reliable?
The price and inventory of AT17C002-10JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C002-10JI is usually 5 days.
3.What payment methods are accepted for AT17C002-10JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C002-10JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C002-10JI?
AT17C002-10JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C002-10JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C002-10JI?
For technical support, including AT17C002-10JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C002-10JI requirements.
6.How does Aetrix verify that AT17C002-10JI is sourced from the original manufacturer or authorized distributors?
All AT17C002-10JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C002-10JI meets industry standards.
7.What is the process for return or replacement of AT17C002-10JI?
All AT17C002-10JI units undergo pre-shipment inspection (PSI). If there is an issue with AT17C002-10JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C002-10JI part is unused and in its original packaging.
Return procedure for AT17C002-10JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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