Microchip Technology AT17C002A-10JC

Overview

AT17C002A-10JC from Atmel is a 2-Mbit serial EEPROM FPGA configuration memory designed for Altera FLEX® devices, operating at 5V ±5% with commercial temperature range (0°C to +70°C), housed in a 20-lead PLCC package, and supporting in-system programming via 2-wire interface for reliable bitstream loading during power-up.

For engineers reviewing the AT17C002A-10JC datasheet, AT17C002A-10JC pinout, AT17C002A-10JC application, or AT17C002A-10JC equivalent, key selection considerations include reset polarity programmability, READY pin timing behavior, cascading support via nCASC/nCS handshaking, and compatibility with Altera EPF10K-series configuration protocols.

Technical Context

The AT17C002A-10JC implements a self-clocked master/slave configuration architecture: it generates its own internal clock for FPGA bitstream delivery, supports daisy-chained operation via nCASC-driven nCS activation, and uses OE as both active-High output enable and programmable active-Low reset signal. Its address counter resets on OE Low and enables DATA output only when nCS is Low and OE is High.

It operates in two distinct modes: FPGA loading mode (SER_EN = High) where DCLK is an output driving the FPGA, and 2-wire programming mode (SER_EN = Low) enabling in-system reprogramming at VCC without external high-voltage supplies. The READY pin provides open-collector power-on reset status indication with tri-state release upon reset completion.

Key Specifications

Pinout & Package

AT17C002A-10JC is packaged in a 20-lead Plastic J-leaded Chip Carrier (PLCC), JEDEC MS-018 AA compliant, with 0.050" lead pitch and body size 9.00 mm × 9.00 mm × 1.20 mm max height.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with AT17LV002A-10JC and AT17C002A-10QC, the AT17C002A-10JC uniquely delivers 5V-native operation in legacy PLCC sockets - essential for drop-in replacement of aging EPC2-based designs without board redesign or voltage rail changes.

Availability

AT17C002A-10JC is available at Aetrix Electronics and suitable for industrial PLCs, FPGA-based motor drives, communications baseband processors, and automated test equipment requiring stable component supply across extended product lifecycles.

Supply support for AT17C002A-10JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation, now part of Microchip Technology, is a semiconductor innovator specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions for industrial and embedded markets.

The AT17A Series - including AT17C002A-10JC - was engineered specifically to replace Altera's EPC configuration EEPROMs, delivering plug-compatible timing, pinout, and protocol support for FLEX-family FPGAs.

FAQ

What is the primary function of the AT17C002A-10JC in an FPGA system?

The AT17C002A-10JC serves as a dedicated 2-Mbit serial EEPROM configuration memory for Altera FLEX® FPGAs. It stores the FPGA's bitstream and autonomously loads it on power-up using its internal oscillator and DCLK output. The AT17C002A-10JC interfaces directly with FPGA control pins (nCS, OE, DATA0) and uses the READY signal to synchronize nCONFIG assertion - eliminating need for external controllers.

Does the AT17C002A-10JC support in-system programming, and how is it enabled?

Yes, the AT17C002A-10JC supports in-system programming via a 2-wire serial interface. Programming mode is activated by driving the SER_EN pin Low while maintaining VCC at 5V. In this mode, the device accepts write commands through the DATA and DCLK pins using I²C-compatible protocol. The AT17C002A-10JC generates internal programming voltages - no external high-voltage supply is needed.

How does the READY pin on the AT17C002A-10JC interact with FPGA configuration timing?

READY is an open-collector output that drives Low during the AT17C002A-10JC's internal power-on reset cycle and tri-states upon completion. It is commonly tied to the FPGA's nCONFIG pin (with pull-up) to hold the FPGA in reset until the EEPROM is ready to begin configuration. The AT17C002A-10JC releases READY before VCC fully stabilizes, so external RC delay may still be recommended for robust nCONFIG timing.

Can multiple AT17C002A-10JC devices be cascaded, and what pins enable this?

Yes, multiple AT17C002A-10JC devices can be daisy-chained for expanded configuration memory. Cascading is enabled by connecting the nCASC output of one device to the nCS input of the next. When the first AT17C002A-10JC finishes transmitting its data, it drives nCASC Low, which activates the second device's nCS and initiates its data output - all synchronized to the master's DCLK.

What is the significance of programmable reset polarity on the AT17C002A-10JC?

The AT17C002A-10JC allows users to program the OE pin's reset polarity (active-Low or active-High) via internal EEPROM bytes. For Altera FLEX devices, active-Low OE is required to match FPGA nCONFIG timing - this setting is programmed during initial device setup and persists across power cycles. The AT17C002A-10JC defaults to active-Low OE after factory programming.