Microchip Technology AT17C020-10JC

Overview

AT17C020-10JC from Atmel is a 2-Mbit (2,097,152 × 1) serial EEPROM FPGA configuration memory in 20-pin PLCC package, operating at 5V ±5% over 0°C to +70°C. It supports Master Serial Mode configuration of Xilinx XC3000/XC4000/XC5200/Spartan/Virtex, Altera FLEX®, ORCA®, and Atmel AT40K/AT6000 FPGAs. Features include programmable reset polarity, system-friendly READY pin, and cascading capability via CEO output.

For engineers reviewing the AT17C020-10JC datasheet, AT17C020-10JC pinout, AT17C020-10JC application, or AT17C020-10JC equivalent, key selection criteria include 5V operation, PLCC-20 packaging, 12.5 MHz max clock frequency, in-system programmability via 2-wire bus, and compatibility with industry-standard FPGA master serial boot protocols.

Technical Context

The AT17C020-10JC implements a serial-access configuration memory architecture optimized for FPGA boot loading in Master Serial Mode. It uses a synchronous clock-driven bitstream delivery protocol where FPGA CCLK drives the EEPROM's CLK input, and DATA output feeds the FPGA's DIN pin. Internal address counters increment on each CLK edge, and reset polarity (active-High or active-Low) is user-programmable via EEPROM bytes.

Cascading is enabled through the CEO output, which asserts Low after the last bit is read to enable the next device's DATA driver. The READY pin provides open-collector power-good indication during power-on reset, and SER_EN controls entry into 2-wire ISP mode-distinct from normal configuration operation.

Key Specifications

Pinout & Package

AT17C020-10JC is housed in a 20-lead Plastic J-leaded Chip Carrier (PLCC-20, package code 20J), with gull-wing leads and body dimensions 9.02 mm × 9.02 mm × 3.56 mm (0.355" × 0.355" × 0.140").

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with AT17LV020-10JC and XC18V02PC44C, the AT17C020-10JC uniquely combines 5V compatibility, programmable reset polarity, hardware READY signaling, and standardized cascading-making it optimal for mixed-vendor FPGA systems requiring field-upgradability and robust power sequencing.

Availability

AT17C020-10JC is available at Aetrix Electronics and suitable for industrial PLC configuration, Xilinx Spartan prototyping, legacy Altera FLEX system boot, and military avionics FPGA initialization requiring stable component supply and long-term obsolescence management.

Supply support for AT17C020-10JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation was a U.S.-based semiconductor company specializing in microcontrollers, nonvolatile memory, and programmable logic solutions before its acquisition by Microchip Technology in 2016.

The AT17 Series was designed specifically as high-density serial configuration EEPROMs for FPGA boot loading, targeting interoperability across Xilinx, Altera, Lucent, and Atmel FPGA families with minimal external components.

FAQ

What is the primary function of the AT17C020-10JC in an FPGA-based system?

The AT17C020-10JC serves as a nonvolatile configuration memory that stores and delivers the bitstream to Field Programmable Gate Arrays during power-up or reset. It operates in Master Serial Mode, synchronizing with the FPGA's CCLK signal to feed configuration data via the DATA pin. Its 2-Mbit capacity supports single large FPGAs or multiple smaller ones, and it is explicitly validated for Xilinx XC3000/XC4000/XC5200/Spartan/Virtex, Altera FLEX®, ORCA®, and Atmel AT40K/AT6000 devices. The AT17C020-10JC ensures deterministic, repeatable FPGA initialization without host processor intervention.

How does the READY pin on the AT17C020-10JC improve system reliability?

The READY pin is an open-collector output that remains low during the AT17C020-10JC's internal power-on reset cycle and transitions to high-impedance once VCC stabilizes within specification. This signal can be connected to the FPGA's INIT or CON pin to delay configuration start until power is fully settled-preventing corrupted bitstream loading due to brown-out conditions. A 4.7 kΩ pull-up resistor is recommended per the datasheet. Because READY is tied directly to the EEPROM's internal reset state-not derived from external monitoring-it provides tighter timing correlation than discrete supervisor ICs, enhancing reliability in noise-sensitive or thermally variable environments. The AT17C020-10JC's READY behavior is consistent across all operating conditions.

Can the AT17C020-10JC be programmed in-circuit, and what interface is required?

Yes, the AT17C020-10JC supports in-system programming (ISP) via a 2-wire serial bus. Programming is enabled by pulling the SER_EN pin low, which places the device into ISP mode independent of CE or RESET/OE states. Data and clock are applied to the DATA and CLK pins respectively, using standard I²C-compatible waveforms. No external high-voltage programming signals are needed-the AT17C020-10JC generates internal programming voltages from the 5V supply. Industry-standard programmers-including Atmel's ATDH2200E-and custom MCU-based programmers can perform read/write/verify cycles. The AT17C020-10JC retains full configuration data integrity during ISP, and programming does not disrupt existing FPGA operation when properly isolated.

What is the significance of programmable reset polarity on the AT17C020-10JC?

Programmable reset polarity allows the AT17C020-10JC's RESET/OE pin to be configured as either active-High or active-Low via internal EEPROM bytes written during programming. This eliminates the need for external inverters when interfacing with FPGAs that assert reset in opposite polarity-such as Xilinx devices (typically active-Low INIT) versus certain Altera configurations (active-High nCONFIG). The setting persists across power cycles and is verified during device initialization. Because the AT17C020-10JC handles polarity internally, system designers avoid layout complexity, BOM cost, and potential timing skew introduced by discrete logic. This feature is supported by all compliant programmers and is documented in Atmel's "Programming Specification for FPGA Configuration EEPROMs".

Is the AT17C020-10JC pin-compatible with other devices in the AT17 family?

Yes, the AT17C020-10JC is pin-compatible with all members of the AT17 Series in the same 20-pin PLCC (20J) package, including AT17C001, AT17C010, AT17LV020, and AT17LV001. Pin functions-including DATA, CLK, RESET/OE, CE, CEO, READY, SER_EN, VCC, and GND-are identical across the family. This allows direct substitution based on voltage (5V vs. 3.3V) and density requirements without PCB redesign. However, electrical differences exist: AT17C variants require 5V ±5%, while AT17LV variants operate at 3.3V ±10%; AC timing parameters also differ, especially maximum clock frequency (12.5 MHz for AT17C020-10JC vs. 7.5 MHz for AT17LV020-10JC in industrial range). The AT17C020-10JC maintains full functional compatibility in 5V systems where timing margins permit.