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Microchip Technology AT17C020-10JI
- Part No.:
- AT17C020-10JI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 20-LCC (J-Lead)
- Datasheet:
-
AT17C020-10JI.pdf
- Description:
- 1C SERIAL CONFIG PROM 2M 20PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:4,506
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Product details
Overview
AT17C020-10JI from Microchip Technology (formerly Atmel) is a 2-Mbit serial EEPROM FPGA configuration memory in 20-pin PLCC, designed to store and load bitstreams for Xilinx XC3000/XC4000/XC5200/Spartan/Virtex, Altera FLEX®, ORCA®, and Atmel AT40K/AT6000 FPGAs. It operates at 5V ±10% over –40°C to +85°C, supports in-system programming via 2-wire bus, and features programmable reset polarity and a system-friendly READY pin.
For engineers reviewing the AT17C020-10JI datasheet, AT17C020-10JI pinout, AT17C020-10JI application, or AT17C020-10JI equivalent, key selection criteria include industrial-temperature operation, cascading capability for multi-FPGA systems, compatibility with Master Serial Mode, low-power standby (<0.75 mA), and PLCC-20 package compatibility across the AT17 family.
Technical Context
The AT17C020-10JI functions as a dedicated serial configuration memory in FPGA Master Serial Mode: CCLK from the FPGA clocks the device, DATA drives the FPGA's DIN, and CEO enables daisy-chained EEPROMs. Its internal address counter auto-increments on each CLK edge and resets upon active RESET/OE or power-up.
It implements a CMOS EEPROM core with open-collector DATA and READY outputs, programmable reset polarity (active-High or active-Low), and SER_EN-controlled 2-wire ISP mode. Standby current is <0.75 mA at 5V when CE is high, and timing is guaranteed up to 12.5 MHz clock frequency under industrial conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 2,097,152 × 1 bit - sufficient to configure one XC4000 or multiple smaller FPGAs (e.g., two XC3000 devices) |
| Supply voltage | 5V ±10% - supports industrial temperature range (–40°C to +85°C) without derating |
| Max clock frequency | 12.5 MHz - enables fast configuration loading compatible with XC4000/XC5200 master clock rates |
| Standby current | <0.75 mA at 5V - reduces system power during FPGA idle or reset states |
| Reset polarity | Programmable (active-High or active-Low) - eliminates need for external inverters in INIT-driven reset schemes |
| READY function | Open-collector power-good indicator - signals FPGA when VCC has stabilized, enabling reliable power-up sequencing |
| Cascading support | CEO output with automatic handoff - allows seamless chaining of multiple AT17C020-10JI devices for larger configurations |
Pinout & Package
AT17C020-10JI is housed in a 20-lead Plastic J-Leaded Chip Carrier (PLCC-20), pin-compatible across the AT17 family and suitable for surface-mount assembly with standard reflow profiles.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DATA (Pin 13) | Bi-directional I/O | Three-state open-collector output during configuration; bidirectional for 2-wire ISP programming |
| CLK (Pin 4) | Input | Drives internal address/bit counters; synchronized to FPGA CCLK for deterministic bitstream delivery |
| RESET/OE (Pin 6) | Input | Programmable reset/enable control - resets address counter when asserted; polarity configurable in EEPROM |
| CE (Pin 8) | Input | Chip enable - disables counters and forces standby mode when high; ignored during SER_EN-low ISP mode |
| CEO (Pin 14) | Output | Chip Enable Output - goes low after last bit read to enable next EEPROM in cascade chain |
| READY (Pin 15) | Output | Open-collector power-good signal - driven low during power-on reset, released when VCC is stable |
| SER_EN (Pin 17) | Input | Serial enable - must be high for FPGA configuration; pulled low to enter 2-wire ISP programming mode |
| VCC (Pin 20) | Power | +5V supply input - supports 5V ±10% operation across industrial temperature range |
| GND (Pin 10) | Ground | Reference ground - requires 0.2 µF decoupling capacitor per datasheet recommendation |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field updates of FPGA configuration bitstreams using standard 2-wire interface without removing the device |
| Cascadable CEO output | Allows daisy-chaining multiple AT17C020-10JI units to support >2-Mbit total configuration storage for large or multi-FPGA systems |
| Programmable reset polarity | Eliminates external logic for FPGA INIT-driven reset synchronization - supports both active-High and active-Low schemes |
| System-friendly READY pin | Provides hardware-level power-good indication to FPGA or system controller, ensuring robust power-up sequencing without software polling |
| PLCC-20 pin compatibility | Ensures mechanical and electrical interoperability across AT17 family variants (e.g., AT17C010, AT17LV020), simplifying BOM consolidation |
Applications
| Industrial PLC Configuration | Xilinx Spartan-Based Motor Drives |
|---|---|
Use Scenario: Configuring FPGA-based motion control logic in factory automation systems operating continuously at ambient temperatures up to 85°C. IC Role / Device Role / Timing Role: Dedicated serial configuration memory providing deterministic bitstream loading at power-up in Master Serial Mode. Use Value: Industrial temperature rating (–40°C to +85°C) and 5V ±10% tolerance ensure reliable operation in electrically noisy, thermally demanding PLC cabinets. | Use Scenario: Loading configuration data into Spartan FPGAs used for real-time PWM generation and encoder interface in servo drive modules. IC Role / Device Role / Timing Role: Synchronous configuration memory clocked by FPGA CCLK, delivering bitstream with ≤50 ns CLK-to-DATA delay (TCAC). Use Value: Guaranteed 12.5 MHz max clock rate and low propagation delays enable sub-millisecond configuration times critical for fast-restart motor control applications. |
| Altera FLEX®-Based Test Equipment | Military-Avionics FPGA Reconfiguration |
Use Scenario: Storing multiple configuration images for FLEX 10K/8000 devices in automated test equipment requiring field-upgradable functionality. IC Role / Device Role / Timing Role: Cascadable configuration memory supporting image selection via CEO handoff between AT17C020-10JI units. Use Value: In-system programmability (via SER_EN) allows remote bitstream updates without hardware intervention or board removal. | Use Scenario: Providing radiation-tolerant, long-life configuration storage for Xilinx Virtex FPGAs in airborne mission computers where reliability and thermal stability are critical. IC Role / Device Role / Timing Role: Nonvolatile configuration memory with programmable reset polarity to synchronize with aircraft power-up sequencing and cold-start requirements. Use Value: Low standby current (<0.75 mA) and wide industrial temp range reduce thermal load and extend operational life in sealed avionics enclosures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV020-10JI | 3.3V operation (3.0–3.6V), lower active current (5 mA), reduced max clock frequency (7.5 MHz industrial) | Targets 3.3V FPGA systems; not suitable for legacy 5V-only designs or high-speed 12.5 MHz configurations | Select only if host FPGA and system supply operate at 3.3V and timing margin permits 7.5 MHz clocking. |
| Xilinx XC18V02 | Pin-compatible 2-Mbit PROM, supports 3.3V/5V, but lacks programmable reset polarity and READY pin | Requires external reset conditioning logic and lacks integrated power-good signaling for autonomous startup | Prefer AT17C020-10JI when READY-driven power sequencing or flexible reset synchronization is required. |
Compared with AT17LV020-10JI and XC18V02, the AT17C020-10JI uniquely delivers 5V industrial operation with programmable reset polarity and a dedicated READY output-enabling simpler, more robust FPGA power-up and reconfiguration in mixed-voltage or thermally demanding environments.
Availability
AT17C020-10JI is available at Aetrix Electronics and suitable for industrial PLCs, motor drives, test equipment, and avionics systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT17C020-10JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel FPGA configuration products, including documentation, programming tools, and long-term supply assurance.
The AT17 series was designed specifically for reliable, low-risk FPGA configuration in industrial and embedded systems - emphasizing ease of integration, in-system update capability, and robust power-up behavior without external support components.
FAQ
What is the operating voltage range for AT17C020-10JI?
The AT17C020-10JI operates at 5V ±10%, supporting 4.5V to 5.5V across its industrial temperature range (–40°C to +85°C). This ensures compatibility with legacy 5V FPGA systems and stable performance under varying line conditions without requiring external regulation beyond standard decoupling.
Does AT17C020-10JI support cascading with other configuration EEPROMs?
Yes, AT17C020-10JI supports hardware cascading via its CEO (Chip Enable Output) pin. When the last bit is read, CEO asserts low to enable the next AT17C020-10JI in the chain, allowing seamless expansion beyond 2 Mbit for multi-FPGA or high-density configurations without additional control logic.
How does the READY pin function in AT17C020-10JI?
The READY pin on AT17C020-10JI is an open-collector output that remains low during power-on reset and transitions to high-impedance once VCC stabilizes. Used with a 4.7 kΩ pull-up, it provides a hardware handshake to the FPGA or system controller, ensuring configuration begins only after valid supply conditions are met.
Can AT17C020-10JI be programmed in-circuit?
Yes, AT17C020-10JI supports in-system programming (ISP) via its 2-wire serial interface. Asserting SER_EN low enables ISP mode, allowing field updates of FPGA configuration bitstreams using industry-standard programmers or Atmel's ATDH2200E - no socket or rework required.
What is the significance of programmable reset polarity in AT17C020-10JI?
Programmable reset polarity in AT17C020-10JI allows the RESET/OE pin to be configured as either active-High or active-Low via internal EEPROM bytes. This eliminates external inverters when interfacing with FPGA INIT pins and enables direct synchronization with diverse FPGA reset architectures - a key advantage over fixed-polarity alternatives like XC18V02.
AT17C020-10JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 20-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 2Mb
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-PLCC (9x9)
AT17C020-10JI FAQ
1.How can I place an order for AT17C020-10JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C020-10JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C020-10JI reliable?
The price and inventory of AT17C020-10JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C020-10JI is usually 5 days.
3.What payment methods are accepted for AT17C020-10JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C020-10JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C020-10JI?
AT17C020-10JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C020-10JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C020-10JI?
For technical support, including AT17C020-10JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C020-10JI requirements.
6.How does Aetrix verify that AT17C020-10JI is sourced from the original manufacturer or authorized distributors?
All AT17C020-10JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C020-10JI meets industry standards.
7.What is the process for return or replacement of AT17C020-10JI?
All AT17C020-10JI units undergo pre-shipment inspection (PSI). If there is an issue with AT17C020-10JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C020-10JI part is unused and in its original packaging.
Return procedure for AT17C020-10JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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