Microchip Technology AT17C020A-10JC

Overview

AT17C020A-10JC from Atmel is a 2-Mbit serial EEPROM FPGA configuration memory designed specifically for Altera FLEX® devices, operating at 5V ±5% over 0°C to 70°C, featuring programmable reset polarity, in-system programmability via 2-wire bus, and cascading support for multi-device configurations.

For engineers reviewing the AT17C020A-10JC datasheet, AT17C020A-10JC pinout, AT17C020A-10JC application, or AT17C020A-10JC equivalent, this device serves as a system-master configuration loader with internal clock generation, READY pin for power-up sequencing, and PLCC-20 packaging optimized for SRAM-based FPGA boot integrity.

Technical Context

The AT17C020A-10JC implements a dedicated serial configuration controller architecture with internal oscillator, address counter, and tri-state DATA output, interfacing directly with Altera FPGA control signals (nCS, OE, DCLK) without external logic. It supports master-mode clock generation and slave-mode daisy-chain handshaking via nCASC/nCS.

Its programming mode is activated by SER_EN low, enabling 2-wire serial write at VCC only; reset polarity is user-programmable in EEPROM bytes. The READY pin provides open-collector power-on reset status indication, synchronized to internal POR timing-not system VCC stabilization.

Key Specifications

Pinout & Package

AT17C020A-10JC is housed in a 20-lead Plastic J-Leaded Chip Carrier (PLCC-20, package code 20J), measuring 0.350" × 0.350" (8.89 mm × 8.89 mm), with gull-wing leads suitable for reflow soldering and socketed prototyping.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with AT17LV020A-10JC and EPC2LC20, the AT17C020A-10JC delivers guaranteed 5V compatibility, higher clock tolerance (12.5 MHz), and active manufacturing support-making it the optimal choice for new 5V FPGA designs requiring sustained component availability and in-system update capability.

Availability

AT17C020A-10JC is available at Aetrix Electronics and suitable for FPGA configuration boot, multi-device bitstream chaining, and legacy EPC2 replacement requiring stable component supply, long-term obsolescence mitigation, and industrial-grade commercial temperature performance.

Supply support for AT17C020A-10JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and programmable logic solutions, with deep expertise in FPGA configuration infrastructure.

The AT17A Series-including AT17C020A-10JC-is engineered exclusively for reliable, self-timed FPGA configuration in SRAM-based programmable logic systems, emphasizing protocol fidelity, daisy-chain scalability, and system-level power sequencing integration.

FAQ

What is the primary function of the AT17C020A-10JC in an FPGA system?

The AT17C020A-10JC serves as a dedicated serial configuration EEPROM that stores and loads bitstream data into Altera FLEX® FPGAs at power-up. It operates autonomously using its internal oscillator to generate DCLK, sequences configuration data onto the DATA pin, and coordinates timing via OE, nCS, and READY signals-eliminating need for external controllers. Its role is strictly configuration memory, not general-purpose EEPROM.

Can the AT17C020A-10JC be used with 3.3V FPGAs?

No-the AT17C020A-10JC is specified only for 5V ±5% operation (VCC = 4.75–5.25 V). It is incompatible with 3.3V FPGA I/O banks. For 3.3V systems, use the pin-compatible AT17LV020A-10JC variant instead. Mixing AT17C020A-10JC with 3.3V logic may cause excessive current leakage, timing violations, or permanent damage due to VIH/VIL level mismatch.

How does the READY pin function in the AT17C020A-10JC?

The READY pin on the AT17C020A-10JC is an open-collector output that is actively driven Low during internal power-on reset and tri-stated upon completion. It is intended to synchronize FPGA nCONFIG assertion but does not track system VCC stabilization-its release occurs before VCC fully settles. A 4.7 kΩ pull-up resistor is required externally. This behavior is fixed and not programmable in the AT17C020A-10JC.

Is the AT17C020A-10JC pin-compatible with Altera EPC2 devices?

Yes-the AT17C020A-10JC is explicitly documented as a direct replacement for Altera EPC2 series EEPROMs (e.g., EPC2LC20), sharing identical PLCC-20 pinout, 5V operation, and serial configuration protocol. Atmel confirms functional and mechanical compatibility, including matching DCLK timing, nCS handshake, and DATA bitstream format-enabling drop-in substitution in legacy designs.

What programming interface does the AT17C020A-10JC support?

The AT17C020A-10JC supports in-system programming via a 2-wire serial interface enabled by pulling SER_EN low. Programming occurs at VCC only-no external high-voltage supply is needed-as internal charge pumps generate required programming voltages. It is programmed using industry-standard programmers or Atmel's ATDH2200E kit; standard I²C controllers cannot be used without protocol translation due to nonstandard addressing and command structure.