Microchip Technology AT17C020A-10JI

Overview

AT17C020A-10JI from Atmel is a 2-Mbit serial EEPROM FPGA configuration memory designed specifically for Altera FLEX® devices, operating at 5V ±10% over -40°C to +85°C industrial temperature range, featuring programmable reset polarity, in-system programmability via 2-wire bus, and PLCC-20 packaging. It serves as a master configuration controller that generates its own clock and drives DCLK to FPGAs during boot.

For engineers reviewing the AT17C020A-10JI datasheet, AT17C020A-10JI pinout, AT17C020A-10JI application, or AT17C020A-10JI equivalent, key selection criteria include industrial-grade voltage tolerance (4.5–5.5 V), cascading support via nCASC, READY pin for power-on reset synchronization, and compatibility with Altera EPF10K-series configuration protocols.

Technical Context

The AT17C020A-10JI implements a dedicated serial configuration architecture with internal oscillator, address counter, and tri-state DATA output controlled by OE (active-High enable / active-Low reset) and nCS (active-Low chip select). Its cascade logic uses nCASC (active-Low) to chain multiple devices, enabling multi-FPGA or high-density configuration sequences without external controllers.

It supports two operational modes: FPGA loading mode (SER_EN = High) and 2-wire programming mode (SER_EN = Low). In loading mode, it functions as a system master-generating DCLK, managing data streaming, and asserting READY during power-on reset. The programmable OE polarity ensures alignment with Altera's active-Low reset requirement when configured for EPF10K devices.

Key Specifications

Pinout & Package

AT17C020A-10JI is housed in a 20-lead Plastic Leaded Chip Carrier (PLCC-20) package per JEDEC MS-018 AA, with gull-wing J-leads suitable for surface-mount assembly and rework-friendly socketing.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with AT17LV020A-10JI and EPC2TC32, the AT17C020A-10JI uniquely combines 5V industrial operation, READY-based reset coordination, and 2-wire in-system programmability - making it optimal for legacy 5V FPGA systems requiring field-upgradable configurations.

Availability

AT17C020A-10JI is available at Aetrix Electronics and suitable for industrial automation, FPGA-based test equipment, and legacy Altera system upgrades requiring stable component supply, long-term lifecycle support, and drop-in EPC2 replacement capability.

Supply support for AT17C020A-10JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in nonvolatile memory, microcontrollers, and FPGA configuration solutions.

The AT17A Series - including AT17C020A-10JI - was engineered to provide robust, self-timed configuration memory for Altera FLEX® FPGAs, emphasizing industrial reliability, cascading flexibility, and system-level integration via READY and SER_EN signals.

FAQ

What is the primary function of the AT17C020A-10JI in an FPGA system?

The AT17C020A-10JI serves as a dedicated configuration memory for Altera FLEX® FPGAs, storing and serially delivering bitstream data during power-up. It operates as a master clock generator (DCLK), manages data sequencing via internal address counter, and provides hardware reset coordination through the READY pin - all without requiring external controllers. Its 2-Mbit capacity supports EPF10K-class devices, and its industrial rating ensures reliability in demanding environments.

How does the READY pin on the AT17C020A-10JI improve system reliability?

The READY pin on the AT17C020A-10JI is an open-collector output that asserts Low during power-on reset and releases (tri-states) once internal initialization completes. This allows designers to tie READY directly to the FPGA's nCONFIG pin (via pull-up), ensuring the FPGA remains held in reset until the AT17C020A-10JI is fully ready to deliver valid configuration data - preventing premature or corrupted configuration attempts due to unstable VCC or internal state.

Can the AT17C020A-10JI be programmed in-circuit, and what interface is required?

Yes, the AT17C020A-10JI supports in-system programming via a 2-wire serial interface activated by pulling SER_EN Low. Programming occurs at nominal VCC (4.5–5.5 V), with internal charge pumps generating required programming voltages - eliminating need for external high-voltage supplies. Industry-standard programmers or Atmel's ATDH2200E kit can be used, and the process preserves full industrial temperature qualification of the AT17C020A-10JI.

What is the significance of the nCASC pin on the AT17C020A-10JI?

The nCASC pin on the AT17C020A-10JI is an active-Low cascade select output that signals end-of-data transmission. In multi-device chains, nCASC from the first AT17C020A-10JI is connected to nCS of the second device, triggering its activation only after the first device completes its data stream. This hardware handshaking eliminates timing dependencies and ensures seamless, glitch-free daisy-chained configuration - essential for systems with FPGAs exceeding 2-Mbit configuration size.

Is the AT17C020A-10JI pin-compatible with Altera EPC2 series EEPROMs?

Yes, the AT17C020A-10JI is a direct pin- and function-compatible replacement for Altera EPC2 configuration EEPROMs, sharing identical PLCC-20 packaging, pinout (including DCLK, DATA, nCS, OE, READY), and AC timing specifications (e.g., TOE ≤35 ns, FMAX = 12.5 MHz). It retains full compatibility with Altera Quartus II tools and EPF10K configuration protocols while adding enhancements like programmable reset polarity and SER_EN-controlled 2-wire programming.