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Microchip Technology AT17C128-10CC
- Part No.:
- AT17C128-10CC
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-TDFN
- Datasheet:
-
AT17C128-10CC.pdf
- Description:
- IC SRL CONFIG EEPROM 128K 8LAP
- Quantity:
- Payment:
- Shipping:
Inventory:1,205
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Product details
Overview
AT17C128-10CC from Microchip Technology (formerly Atmel) is a 128 Kbit (131,072 × 1-bit) serial EEPROM FPGA configuration memory with 5V ±5% supply operation, 8 MHz max clock frequency in cascaded mode, and programmable reset polarity. It interfaces directly with Xilinx XC4000/SPARTAN®, Altera FLEX®, and Atmel AT40K/AT6000 FPGAs in Master Serial Mode for power-up configuration loading.
For engineers reviewing the AT17C128-10CC datasheet, AT17C128-10CC pinout, AT17C128-10CC application, or AT17C128-10CC equivalent, key selection criteria include cascading support via CEO output, in-system programmability via 2-wire bus, write-protection capability, low-power standby current (75 µA), and compatibility with industrial temperature range (–40°C to +85°C).
Technical Context
The AT17C128-10CC operates in FPGA Master Serial Mode, where the FPGA's CCLK drives the EEPROM's CLK input and DATA output feeds the FPGA's DIN. Its internal address counter advances on each CLK edge, enabling sequential bitstream delivery without external control logic.
Cascading is supported exclusively for AT17C128/256 variants: the CEO output asserts low after final bit read to enable the next device's DATA line. Reset polarity (active-high or active-low) is user-programmable via EEPROM byte, eliminating need for external inverters during FPGA reset synchronization.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 131,072 × 1-bit (128 Kbit) nonvolatile configuration storage |
| Supply voltage | 5V ±5% - ensures compatibility with legacy 5V FPGA systems and eliminates level-shifting requirements |
| Max clock frequency | 8 MHz in cascaded mode - sets timing budget for multi-device daisy-chain configuration sequences |
| Standby current | 75 µA at 5V - enables low-power system sleep states without losing configuration state |
| Operating temperature | –40°C to +85°C - supports industrial-grade embedded FPGA deployments |
| Write protection | Hardware-enabled via WP pin - prevents accidental overwrite of critical configuration data during operation |
| Reset polarity | Programmable (active-high or active-low) - matches FPGA reset signal behavior without external logic |
Pinout & Package
AT17C128-10CC is available in 20-lead PLCC (package code CC) with 0.400" body width and J-lead geometry per JEDEC MS-018 AA. Pin 1 is marked by corner notch; leads are numbered counterclockwise starting from top-left.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | DATA | Three-state bidirectional I/O - delivers configuration bitstream to FPGA DIN; open-collector during programming |
| 2 | CLK | Input - synchronous clock from FPGA CCLK; increments internal address/bit counter on rising edge |
| 3 | (WP) RESET/OE | Input - dual-function pin: active-low reset/enable (when SER_EN = High); write-protect (when CE = Low) |
| 4 | CE | Input - chip enable; high disables counters and forces standby mode (<75 µA) |
| 5 | GND | Ground reference - requires 0.2 µF decoupling capacitor to VCC for noise immunity |
| 6 | CEO (A2) | Output - cascading enable signal; goes low after last bit read to trigger next EEPROM in chain |
| 7 | SER_EN | Input - serial programming enable; must be high during FPGA configuration, low to enter 2-wire ISP mode |
| 8 | VCC | Power supply - accepts 5V ±5%; powers internal charge pump for programming |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field updates via 2-wire serial bus without removing device from PCB |
| Cascadable CEO output | Supports daisy-chained configuration of multiple FPGAs or higher-density arrays using single clock domain |
| Programmable reset polarity | Eliminates external inverter components by allowing EEPROM reset behavior to match FPGA reset signal logic |
| Emulation of AT24CXXX EEPROMs | Allows reuse of existing serial EEPROM programming infrastructure and firmware drivers |
| Low-power standby mode | Reduces system quiescent current during idle periods while retaining full configuration memory integrity |
Applications
| Industrial PLC Configuration | Aerospace Avionics Boot Memory |
|---|---|
|
Use Scenario: Reconfigurable logic in programmable logic controllers requires reliable, nonvolatile storage of safety-critical FPGA bitstreams across power cycles and environmental stress. IC Role / Device Role / Timing Role: AT17C128-10CC serves as primary configuration loader in Master Serial Mode, delivering bitstream on power-up under industrial temperature (-40°C to +85°C) and EMI conditions. Use Value: Programmable reset polarity ensures deterministic re-synchronization after watchdog-triggered resets, preventing partial configuration load failures. |
Use Scenario: Radiation-tolerant avionics systems use FPGAs for real-time signal processing; configuration memory must survive thermal cycling and maintain data integrity over 10+ years. IC Role / Device Role / Timing Role: AT17C128-10CC provides certified 128 Kbit configuration storage with 5V operation compatible with legacy aerospace power architectures. Use Value: Cascading CEO output enables redundant dual-FPGA configurations without adding timing-critical glue logic or increasing board area. |
| Telecom Baseband Processing | Medical Imaging FPGA Platform |
|
Use Scenario: Remote radio units require hot-swappable FPGA reconfiguration for protocol updates; memory must support in-field programming without system downtime. IC Role / Device Role / Timing Role: AT17C128-10CC operates in ISP mode (SER_EN = Low) to accept new bitstreams via 2-wire interface while system remains powered. Use Value: Write-protection (WP) pin prevents accidental corruption during firmware update sequences, ensuring bitstream integrity before activation. |
Use Scenario: MRI and CT scanner control boards use FPGAs for high-speed data acquisition; configuration memory must meet medical-grade reliability and traceability standards. IC Role / Device Role / Timing Role: AT17C128-10CC stores validated bitstreams for FDA-cleared imaging algorithms, loaded automatically at power-on in Master Serial Mode. Use Value: Low standby current (75 µA) minimizes heat generation near sensitive analog front-end circuitry, preserving signal-to-noise ratio. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10CC | 3.3V ±10% supply; slower max clock (8 MHz cascaded, 10 MHz standalone); higher AC delays (e.g., TCAC = 75 ns vs. 55 ns) | Targets modern low-voltage FPGA platforms; incompatible with 5V-only systems | Select AT17LV128-10CC only when system VCC is strictly 3.3V and timing margins allow increased propagation delays. |
| XCR3256XL-10TQ144I | Integrated CPLD with on-chip configuration memory; no external EEPROM required; 3.3V operation only | Eliminates discrete configuration memory but fixes bitstream to device; not field-upgradable without reprogramming CPLD | Choose XCR3256XL-10TQ144I for cost-sensitive, fixed-function designs where configuration updates are rare and board space is constrained. |
Compared with AT17LV128-10CC, AT17C128-10CC delivers tighter timing (55 ns CLK-to-DATA), higher noise immunity (5V logic levels), and guaranteed compatibility with legacy 5V FPGA families; versus XCR3256XL-10TQ144I, it retains full field-upgradability and avoids CPLD resource constraints.
Availability
AT17C128-10CC is available at Aetrix Electronics and suitable for industrial PLCs, aerospace avionics, telecom base stations, medical imaging systems, and test equipment requiring stable component supply across extended lifecycle commitments.
Supply support for AT17C128-10CC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product support, documentation, and manufacturing continuity for the AT17 series.
The AT17C/LV family was designed specifically for FPGA configuration storage, emphasizing simplicity of interface, cascading scalability, and robustness in industrial environments.
FAQ
What is the maximum clock frequency supported by AT17C128-10CC in cascaded configuration?
The AT17C128-10CC supports a maximum input clock frequency of 8 MHz when used in cascaded mode, as specified in its AC characteristics table for cascading operation. This limit ensures reliable CEO assertion timing and inter-device handoff between chained AT17C128-10CC devices. Exceeding 8 MHz may cause data misalignment or incomplete configuration loading in multi-device chains.
Does AT17C128-10CC support in-system programming, and what interface is required?
Yes, AT17C128-10CC supports in-system programming via a 2-wire serial bus. Programming is enabled by pulling SER_EN low, after which standard I²C-compatible protocols can be used. The AT17C128-10CC does not require external high-voltage programming signals - all necessary voltages are generated internally from the 5V VCC supply.
Can AT17C128-10CC be used with Xilinx Spartan FPGAs, and what connection is required?
Yes, AT17C128-10CC is explicitly compatible with Xilinx SPARTAN® FPGAs in Master Serial Mode. The FPGA's CCLK pin connects to AT17C128-10CC CLK; AT17C128-10CC DATA connects to FPGA DIN; and AT17C128-10CC CE and RESET/OE are driven by FPGA control pins per Atmel's recommended interface schematics.
What is the purpose of the CEO pin on AT17C128-10CC, and how is it used?
The CEO (Chip Enable Output) pin on AT17C128-10CC signals completion of its configuration bitstream by asserting low on the clock cycle following the last bit read. In cascaded setups, this low signal enables the CE input of the next AT17C128-10CC in the chain, allowing seamless daisy-chained configuration of multiple FPGAs or larger memory requirements.
Is the reset polarity of AT17C128-10CC configurable, and how is it programmed?
Yes, the reset polarity of AT17C128-10CC is programmable as either active-high or active-low via a dedicated EEPROM byte. Programming is performed using industry-standard programmers or Atmel's ATDH2200E kit during initial programming or field updates - no hardware modifications are needed to change reset behavior.
AT17C128-10CC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-TDFN
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-LAP (6x6)
AT17C128-10CC FAQ
1.How can I place an order for AT17C128-10CC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C128-10CC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C128-10CC reliable?
The price and inventory of AT17C128-10CC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10CC is usually 5 days.
3.What payment methods are accepted for AT17C128-10CC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10CC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C128-10CC?
AT17C128-10CC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C128-10CC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C128-10CC?
For technical support, including AT17C128-10CC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10CC requirements.
6.How does Aetrix verify that AT17C128-10CC is sourced from the original manufacturer or authorized distributors?
All AT17C128-10CC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10CC meets industry standards.
7.What is the process for return or replacement of AT17C128-10CC?
All AT17C128-10CC units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10CC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C128-10CC part is unused and in its original packaging.
Return procedure for AT17C128-10CC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17C128-10CC Tags
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AT17LV512A-10PU
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EPCQ4ASI8N
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AT17LV256-10PU
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AT17LV256-10NU
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EPCQ16ASI8N
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EPCQ32ASI8N
Intel
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EPCQ64ASI16N
Intel
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EPCQ128ASI16N
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AT17LV512A-10JU
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AT17LV512-10JU
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AT17LV010-10JU
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