Microchip Technology AT17C128-10JC

Overview

AT17C128-10JC from Atmel is a 128K-bit (131,072 × 1) serial EEPROM FPGA configuration memory with 5V ±5% supply operation, programmable reset polarity, and cascading CEO output for multi-FPGA daisy-chain loading in Master Serial Mode. It supports in-system programming via 2-wire bus and interfaces directly with Xilinx XC4000/SPARTAN®, Altera FLEX®, and Atmel AT40K/AT6000 FPGAs.

For engineers reviewing the AT17C128-10JC datasheet, AT17C128-10JC pinout, AT17C128-10JC application, or AT17C128-10JC equivalent, key selection criteria include 128K-bit capacity, PLCC-20 package compatibility, 8 MHz max clock frequency in cascade mode, write-protection via WP input, and programmable active-high/active-low RESET/OE polarity.

Technical Context

The AT17C128-10JC implements a serial-access configuration memory architecture optimized for FPGA Master Serial Mode bootloading, where CLK drives internal address/bit counters and DATA outputs configuration bitstream to FPGA DIN. Its CEO output enables daisy-chained cascading only for 128K/256K variants - AT17C128-10JC asserts CEO low after final bit read to enable next device's DATA driver.

RESET/OE polarity is user-programmable via EEPROM byte; SER_EN must be high during FPGA configuration and pulled low only for 2-wire ISP. CE controls standby mode (<75 µA at 5V), while WP enables block-level write protection when CE is low and SER_EN is low.

Key Specifications

Pinout & Package

AT17C128-10JC is supplied in a 20-lead Plastic J-leaded Chip Carrier (PLCC) package with 0.400" body width, JEDEC MS-018 AA compliant footprint, and surface-mount J-lead geometry.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with AT17C128-10PC, AT17C128-10JC provides cascading capability and surface-mount compatibility; compared with AT17LV128-10JC, it delivers higher noise immunity and direct compatibility with legacy 5V FPGA families like XC4000 and AT6000.

Availability

AT17C128-10JC is available at Aetrix Electronics and suitable for FPGA configuration bootloading, industrial control system initialization, reconfigurable test equipment, and multi-device daisy-chain applications requiring stable component supply across extended temperature ranges.

Supply support for AT17C128-10JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and programmable logic solutions.

The AT17 Series was designed specifically to provide cost-effective, serial-access configuration memory for SRAM-based FPGAs, emphasizing ease of integration, in-system programmability, and cascading scalability.

FAQ

What is the maximum clock frequency supported by AT17C128-10JC in cascaded configuration?

The AT17C128-10JC supports a maximum input clock frequency of 8 MHz when used in cascaded mode, as specified in the AC Characteristics table for AT17C128 When Cascading under 5V ±5% commercial conditions. This timing ensures reliable CEO assertion and inter-device handoff without bitstream corruption. The AT17C128-10JC must be operated within this limit when chained with other AT17C/LV128 or AT17C/LV256 devices.

Does AT17C128-10JC support in-system programming, and what interface is required?

Yes, AT17C128-10JC supports in-system programming via a 2-wire serial bus. Programming is enabled by pulling SER_EN low, after which standard I²C-compatible protocols can be used. No external high-voltage programming signals are needed-the AT17C128-10JC generates required programming voltages internally. This capability allows field updates without removing the device from the PCB.

Can AT17C128-10JC be used with Xilinx Spartan FPGAs, and what interface signals are required?

Yes, AT17C128-10JC is explicitly compatible with Xilinx SPARTAN® FPGAs per Atmel's documentation. Required interface signals are DATA (drives FPGA DIN), CLK (driven by FPGA CCLK), CE (tied to FPGA CON or controlled independently), and RESET/OE (programmable polarity, tied to FPGA reset or CON). CEO is used only when cascading additional AT17C128-10JC devices.

What is the purpose of the CEO pin on AT17C128-10JC, and how is it used in practice?

The CEO (Chip Enable Output) pin on AT17C128-10JC goes low on the clock cycle immediately following the last configuration bit read. In cascaded setups, this signal drives the CE input of the next AT17C128-10JC (or AT17C256), enabling its DATA output to continue the bitstream. CEO remains low while CE and OE are both low, then follows CE until OE goes high-ensuring seamless handoff between devices without gaps or overlaps in data delivery.

How does the programmable reset polarity feature work on AT17C128-10JC?

The reset polarity of AT17C128-10JC is programmed into a dedicated EEPROM byte using industry-standard programmers or Atmel's ATDH2200E kit. Once set, RESET/OE functions as either active-high or active-low-eliminating the need for external inverters. This setting determines whether a high or low level on the pin resets internal address counters during FPGA reconfiguration, ensuring synchronization even after external system resets.