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Microchip Technology AT17C128-10NC
- Part No.:
- AT17C128-10NC
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT17C128-10NC.pdf
- Description:
- IC EEPROM FPGA 128KB 8-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:1,271
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Product details
Overview
AT17C128-10NC from Atmel is a 128K-bit (131,072 × 1) serial EEPROM FPGA configuration memory operating at 5V ±5% with 10 MHz max clock frequency, programmable reset polarity, and cascading CEO output for multi-FPGA daisy-chain configurations in industrial temperature range (–40°C to +85°C). It interfaces directly with Xilinx XC4000/SPARTAN®, Altera FLEX®, and Atmel AT40K/AT6000 FPGAs via master serial mode.
For engineers reviewing the AT17C128-10NC datasheet, AT17C128-10NC pinout, AT17C128-10NC application, or AT17C128-10NC equivalent, key selection criteria include cascading support (CEO), in-system programmability (SER_EN), write-protection (WP/RESET/OE), standby current (≤150 µA), and compatibility with commercial/industrial FPGA configuration protocols.
Technical Context
The AT17C128-10NC implements a serial-access EEPROM architecture optimized for FPGA configuration loading in Master Serial Mode, where the FPGA's CCLK drives the device's CLK input and DATA feeds the FPGA's DIN. Its internal address counter auto-increments on each CLK edge during read cycles, and supports cascading via CEO output that asserts low after final bit read to enable next EEPROM in chain.
Reset polarity is user-programmable via EEPROM byte; RESET/OE functions as active-high or active-low depending on configuration. SER_EN enables 2-wire programming mode (low) and must be held high during normal FPGA configuration. CE controls standby mode (high = ≤150 µA ICCS), while WP enables block-level write protection only during programming mode.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 131,072 × 1-bit (128 Kbit) nonvolatile EEPROM storage for full FPGA configuration bitstreams |
| Supply voltage | 5V ±5% - compatible with standard 5V FPGA I/O domains and eliminates level-shifting requirements |
| Max clock frequency | 10 MHz - supports fast configuration load times for industrial-grade FPGAs without timing margin violation |
| Standby current | ≤150 µA at 5V - enables low-power system sleep states while retaining configuration readiness |
| Operating temperature | –40°C to +85°C - qualified for industrial embedded control, motor drives, and telecom infrastructure |
| Cascading support | CEO output with 55–60 ns delay - enables daisy-chained configuration of multiple FPGAs using single CCLK source |
| Reset polarity | Programmable active-high or active-low - allows synchronization with FPGA reset assertion timing across diverse board designs |
Pinout & Package
AT17C128-10NC is available in 20-lead PLCC (20J), 20-lead SOIC (20S), 8-pin PDIP (8P3), and 8-lead SOIC (8S1) packages. The -10NC suffix denotes 20-lead PLCC package, industrial temperature grade, and 10 ns AC timing grade.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DATA | I/O | Three-state open-collector bidirectional data line - drives FPGA DIN during configuration; used for 2-wire programming when SER_EN = low |
| CLK | I | FPGA CCLK-synchronized clock input - increments internal address/bit counter on rising edge during read; required for all configuration cycles |
| RESET/OE | I | Programmable polarity input - resets address counter when asserted; also serves as output enable for DATA when CE = low |
| CE | I | Chip Enable - high disables counters and forces ≤150 µA standby mode; low enables read operation and DATA driver activation |
| GND | Power | Ground reference - requires 0.2 µF decoupling capacitor per datasheet recommendation |
| CEO | O | Chip Enable Output - goes low one clock after last bit read; enables next cascaded AT17C128-10NC in daisy-chain topology |
| SER_EN | I | Serial Enable - must be high during FPGA configuration; low enables 2-wire ISP mode for field reprogramming |
| VCC | Power | +5V supply pin - powers EEPROM core and I/O buffers; supports 5V ±5% tolerance for industrial reliability |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enabled via SER_EN pin - allows field updates of FPGA configuration bitstreams without socket removal or dedicated programmers |
| Cascadable CEO output | Dedicated output with 55–60 ns propagation delay - eliminates external logic for multi-device daisy-chain configuration of large FPGA arrays |
| Programmable reset polarity | User-configurable EEPROM byte - ensures deterministic sync with FPGA reset timing regardless of board-level reset circuit topology |
| Write protection (WP) | Hardware-enabled block lock - prevents accidental overwrite of critical configuration sectors during power-up or debug sessions |
| Low-power standby mode | ≤150 µA ICCS at 5V - reduces system-level quiescent power in always-on industrial controllers without sacrificing configuration retention |
Applications
| Industrial PLC Configuration | Xilinx SPARTAN® FPGA Boot |
|---|---|
Use Scenario: Reconfigurable logic modules in programmable logic controllers require persistent, tamper-resistant bitstream storage across power cycles and firmware updates. IC Role / Device Role / Timing Role: AT17C128-10NC serves as primary configuration memory, loaded by SPARTAN-3 FPGA in Master Serial Mode upon power-up or watchdog-triggered reboot. Use Value: 128K-bit capacity stores full gate array configuration; industrial temp rating ensures reliability in factory-floor enclosures with ambient swings up to 85°C. | Use Scenario: Cost-sensitive embedded vision systems use SPARTAN FPGAs for real-time image preprocessing, requiring fast, deterministic boot from nonvolatile memory. IC Role / Device Role / Timing Role: AT17C128-10NC provides serial configuration data to SPARTAN-2/3 FPGA via CCLK-synchronized DATA stream, with CEO unused (standalone mode). Use Value: 10 MHz max clock supports sub-100 ms configuration time; 5V operation matches legacy 5V I/O rails common in industrial camera modules. |
| Altera FLEX® Daisy Chain | Motor Drive FPGA Initialization |
Use Scenario: Multi-axis servo drives integrate multiple FLEX 10K FPGAs for axis-specific motion control, requiring coordinated configuration from shared memory resources. IC Role / Device Role / Timing Role: AT17C128-10NC acts as first-stage configurator in cascade chain, with CEO driving CE of second AT17C128-10NC to extend total configuration capacity beyond 128K bits. Use Value: Cascading eliminates need for larger single-package EEPROMs; identical pinout across PLCC/SOIC variants simplifies PCB layout reuse. | Use Scenario: High-reliability motor inverters use FPGAs for PWM generation and fault monitoring, demanding robust configuration recovery after brownout events. IC Role / Device Role / Timing Role: AT17C128-10NC stores safety-critical configuration and is reset synchronously with FPGA via programmable active-low RESET/OE tied to MCU-controlled reset line. Use Value: Programmable reset polarity ensures immediate address pointer reset on MCU-initiated reboot, guaranteeing clean reconfiguration without bitstream corruption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10NC | 3.3V operation (3.0–3.6V), lower ICCA (5 mA), reduced FMAX (8 MHz), same 128K-bit density and CEO functionality | Targeted for 3.3V FPGA families (e.g., Xilinx Virtex-E, Altera APEX); not suitable for 5V-only systems | Select when interfacing with 3.3V FPGAs and lower power consumption is prioritized over speed |
| AT17C256-10NC | 256K-bit density (262,144 × 1), identical 5V/industrial spec, same pinout and AC timing except FMAX = 10 MHz (cascaded) vs. 12.5 MHz (standalone) | Required for larger FPGAs (e.g., Xilinx XC4025E, Altera FLEX 8000) needing >128K configuration bits | Select when configuration bitstream exceeds 128K; maintains full pin and protocol compatibility |
Compared with AT17LV128-10NC, the AT17C128-10NC delivers higher speed (10 MHz vs. 8 MHz) and 5V compatibility but consumes more active current; versus AT17C256-10NC, it offers cost and space savings for smaller FPGAs without sacrificing industrial temperature support or cascading capability.
Availability
AT17C128-10NC is available at Aetrix Electronics and suitable for industrial PLCs, FPGA-based motor drives, Xilinx SPARTAN® boot systems, and Altera FLEX® daisy-chain configurations requiring stable component supply across extended product lifecycles.
Supply support for AT17C128-10NC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions for industrial and embedded markets.
The AT17 Series was designed specifically as serial configuration EEPROMs for Field Programmable Gate Arrays, targeting reliable, low-cost, and pin-compatible bitstream storage across multiple FPGA vendors and densities.
FAQ
What is the maximum clock frequency supported by the AT17C128-10NC during FPGA configuration?
The AT17C128-10NC supports a maximum input clock frequency of 10 MHz when used in cascaded configuration mode, as specified in its AC characteristics table for industrial temperature range. This timing ensures reliable synchronization with FPGA CCLK inputs in multi-device chains while maintaining setup/hold margins. The AT17C128-10NC achieves this performance using Atmel's low-power CMOS EEPROM process and optimized internal counter logic.
Does the AT17C128-10NC support in-system programming, and how is it enabled?
Yes, the AT17C128-10NC supports in-system programming (ISP) via its 2-wire serial interface. ISP is enabled by pulling the SER_EN pin low, which places the device into programming mode independent of CE or RESET/OE states. During ISP, the AT17C128-10NC accepts write commands and data through the DATA line synchronized to CLK, with internal charge pumps generating required programming voltages - no external high-voltage supply is needed.
Can the AT17C128-10NC be used in a daisy-chain configuration with other AT17 series devices?
Yes, the AT17C128-10NC supports daisy-chain configuration exclusively through its CEO (Chip Enable Output) pin, which asserts low one clock cycle after the final bit is read. This signal directly drives the CE input of the next AT17C128-10NC or AT17C256-10NC in the chain. The AT17C128-10NC cannot accept CEO input - it functions only as a cascade initiator or middle node, never as the final device in a chain.
What does the "-10NC" suffix indicate in the AT17C128-10NC part number?
Within the AT17C128 family, the "-10NC" suffix specifies three attributes: "10" denotes the AC timing grade (10 ns propagation delays), "N" indicates the 20-lead PLCC package (20J), and "C" identifies the industrial temperature range (–40°C to +85°C). This distinguishes it from variants like AT17C128-10PC (8-pin PDIP, industrial) or AT17C128-10SC (20-lead SOIC, industrial), all sharing identical electrical functionality.
How does the programmable reset polarity feature work in the AT17C128-10NC?
The AT17C128-10NC allows users to configure RESET/OE as either active-high or active-low by programming a dedicated EEPROM byte using industry-standard algorithms. This setting determines whether a high or low logic level on the RESET/OE pin resets the internal address counter - enabling precise alignment with FPGA reset timing requirements without external inverters. The AT17C128-10NC retains this setting across power cycles.
AT17C128-10NC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT17C128-10NC FAQ
1.How can I place an order for AT17C128-10NC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C128-10NC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C128-10NC reliable?
The price and inventory of AT17C128-10NC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10NC is usually 5 days.
3.What payment methods are accepted for AT17C128-10NC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10NC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C128-10NC?
AT17C128-10NC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C128-10NC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C128-10NC?
For technical support, including AT17C128-10NC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10NC requirements.
6.How does Aetrix verify that AT17C128-10NC is sourced from the original manufacturer or authorized distributors?
All AT17C128-10NC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10NC meets industry standards.
7.What is the process for return or replacement of AT17C128-10NC?
All AT17C128-10NC units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10NC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C128-10NC part is unused and in its original packaging.
Return procedure for AT17C128-10NC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17C128-10NC Tags
-
AT17LV512A-10PU
Microchip Technology
-
EPCQ4ASI8N
Intel
-
AT17LV256-10PU
Microchip Technology
-
AT17LV256-10NU
Microchip Technology
-
EPCQ16ASI8N
Intel
-
AT17LV010-10PU
Microchip Technology
-
EPCQ32ASI8N
Intel
-
EPCQ64ASI16N
Intel
-
EPCQ128ASI16N
Intel
-
AT17LV512A-10JU
Microchip Technology
-
AT17LV512-10JU
Microchip Technology
-
AT17LV010-10JU
Microchip Technology
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