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Home > Products > Integrated Circuits (ICs) > Memory > Configuration PROMs for FPGAs

Microchip Technology AT17C128-10NI

Name: AT17C128-10NI
Brand: Microchip Technology
SKU: AT17C128-10NI
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT17C128-10NI

Manufacturer:: Microchip Technology

Category:: Configuration PROMs for FPGAs

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: AT17C128-10NI.pdf

Description:: IC EEPROM FPGA 128KB 8-SOIC

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Product details

Overview

AT17C128-10NI from Microchip Technology (formerly Atmel) is a 128 Kbit (131,072 × 1-bit) serial EEPROM FPGA configuration memory with 5V ±10% industrial supply support (−40°C to +85°C), 8 MHz max clock frequency in cascaded mode, and programmable reset polarity. It interfaces directly with SRAM-based FPGAs including Xilinx XC4000/SPARTAN®, Altera FLEX®, and Atmel AT40K/AT6000 via master serial mode for automatic power-up configuration.

For engineers reviewing the AT17C128-10NI datasheet, AT17C128-10NI pinout, AT17C128-10NI application, or AT17C128-10NI equivalent, key selection criteria include cascading capability (CEO output), in-system programmability via 2-wire bus, write-protection control (WP input), low-power standby current (≤150 µA), and compatibility with industry-standard FPGA configuration protocols.

Technical Context

The AT17C128-10NI operates in master serial mode where FPGA CCLK drives its CLK input and DATA output feeds FPGA DIN. Its CEO output enables daisy-chain cascading with other AT17C/LV128 or AT17C/LV256 devices-critical for multi-FPGA systems or larger configuration images. The device uses internal address counters synchronized to CE and RESET/OE inputs, with programmable reset polarity eliminating external inverters.

It supports two distinct operational modes: normal configuration mode (SER_EN = High) and 2-wire serial programming mode (SER_EN = Low). In programming mode, SER_EN enables access to internal EEPROM registers for setting reset polarity and write protection, using only VCC-supplied voltage-no external high-voltage programming required.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	131,072 × 1-bit (128 Kbit) nonvolatile EEPROM storage for full FPGA configuration bitstreams
Supply voltage	5V ±10% - supports industrial temperature range (−40°C to +85°C) without derating
Max clock frequency	8 MHz in cascaded mode - ensures reliable timing margin when chaining multiple AT17C128-10NI devices
Standby current	≤150 µA at 5V - enables low-power system sleep states without losing configuration state
Reset polarity	Programmable active-high or active-low - eliminates need for external level-shifting or inversion circuitry
Write protection	Hardware-enabled via WP pin - prevents accidental overwrite of critical configuration blocks during operation
Cascading support	CEO output with defined timing (TOCK ≤60 ns) - enables deterministic multi-device read-back sequencing

Pinout & Package

AT17C128-10NI is available in 20-lead PLCC (20J), 20-lead SOIC (20S), 8-pin PDIP (8P3), and 8-lead SOIC (8S1) packages. The industrial-grade -10NI suffix applies identically across all four package types per Atmel ordering documentation.

Pin/Terminal	Circuit Role	Design Meaning
DATA	I/O bidirectional open-collector	Drives FPGA DIN during configuration; used for 2-wire serial programming when SER_EN = Low
CLK	Input	Synchronizes internal address/bit counter; driven by FPGA CCLK in master serial mode
RESET/OE	Input	Resets internal address counter when asserted; polarity programmable to match FPGA reset behavior
CE	Input	Enables data output driver and controls standby entry; high level forces ≤150 µA low-power state
GND	Ground reference	0.2 µF decoupling capacitor recommended between GND and VCC for noise immunity
CEO	Output	Chains to CE of next AT17C/LV128/256 device; asserts low after final bit, enabling deterministic cascade handoff
SER_EN	Input	High = normal configuration mode; Low = enters 2-wire serial programming mode (no external VPP needed)
VCC	Power supply	5V ±10% input; powers all logic and EEPROM array; no separate programming voltage required

Key Features

Feature	Design Value
In-system programmability	2-wire serial interface (SER_EN-controlled) allows field updates without removing device from PCB
Cascadable architecture	CEO output timing (TOCK ≤60 ns) guarantees reliable handoff between AT17C128-10NI units in daisy-chain configurations
Programmable reset polarity	EEPROM byte configuration eliminates need for external inverters or pull-up/pull-down networks
FPGA protocol compatibility	Native support for Xilinx XC4000/SPARTAN®, Altera FLEX®, Lucent ORCA®, and Atmel AT40K/AT6000 master serial mode
Hardware write protection	WP pin disables writes to lowest memory block when high - prevents corruption of boot-critical configuration data

Applications

Industrial PLC Configuration	Xilinx SPARTAN FPGA Boot
Use Scenario: Reconfigurable logic modules in factory automation controllers require persistent, tamper-resistant bitstream storage across power cycles and firmware updates. IC Role / Device Role / Timing Role: AT17C128-10NI serves as primary configuration memory, delivering bitstream to Xilinx SPARTAN FPGA on power-up via master serial interface with precise CEO-to-CE handoff timing. Use Value: Industrial temperature rating (−40°C to +85°C) and 150 µA standby current ensure reliability in uncontrolled cabinet environments while minimizing thermal load.	Use Scenario: Cost-sensitive embedded vision systems use SPARTAN FPGAs for real-time image preprocessing, requiring fast, deterministic configuration loading. IC Role / Device Role / Timing Role: AT17C128-10NI provides 128 Kbit storage with 8 MHz cascaded clock support, enabling dual-FPGA configurations where CEO of first unit triggers second unit's CE. Use Value: Programmable reset polarity aligns with SPARTAN's active-low PROG_B signal, eliminating discrete logic and reducing BOM count.
Altera FLEX-Based Motor Drive	Multi-FPGA Telecommunications Shelf
Use Scenario: Variable-frequency motor drives implement safety-critical logic in Altera FLEX FPGAs, demanding secure, field-upgradable configuration storage. IC Role / Device Role / Timing Role: AT17C128-10NI stores configuration data and supports hardware write protection (WP pin) to prevent unauthorized modification during runtime. Use Value: 5V ±10% supply tolerance matches legacy industrial power rails; low-power standby mode extends uptime in battery-backed systems.	Use Scenario: High-density telecom line cards integrate multiple FPGAs for packet processing, requiring scalable configuration memory across 4–8 devices. IC Role / Device Role / Timing Role: AT17C128-10NI units are cascaded using CEO→CE interconnect, with TOCE ≤60 ns ensuring setup time compliance across backplane trace lengths. Use Value: Pin-compatible PLCC/SOIC packaging allows layout reuse across density variants (64K/128K/256K), simplifying design migration.

Industrial PLC Configuration

Xilinx SPARTAN FPGA Boot

Use Scenario: Reconfigurable logic modules in factory automation controllers require persistent, tamper-resistant bitstream storage across power cycles and firmware updates.

IC Role / Device Role / Timing Role: AT17C128-10NI serves as primary configuration memory, delivering bitstream to Xilinx SPARTAN FPGA on power-up via master serial interface with precise CEO-to-CE handoff timing.

Use Value: Industrial temperature rating (−40°C to +85°C) and 150 µA standby current ensure reliability in uncontrolled cabinet environments while minimizing thermal load.

Use Scenario: Cost-sensitive embedded vision systems use SPARTAN FPGAs for real-time image preprocessing, requiring fast, deterministic configuration loading.

IC Role / Device Role / Timing Role: AT17C128-10NI provides 128 Kbit storage with 8 MHz cascaded clock support, enabling dual-FPGA configurations where CEO of first unit triggers second unit's CE.

Use Value: Programmable reset polarity aligns with SPARTAN's active-low PROG_B signal, eliminating discrete logic and reducing BOM count.

Altera FLEX-Based Motor Drive

Multi-FPGA Telecommunications Shelf

Use Scenario: Variable-frequency motor drives implement safety-critical logic in Altera FLEX FPGAs, demanding secure, field-upgradable configuration storage.

IC Role / Device Role / Timing Role: AT17C128-10NI stores configuration data and supports hardware write protection (WP pin) to prevent unauthorized modification during runtime.

Use Value: 5V ±10% supply tolerance matches legacy industrial power rails; low-power standby mode extends uptime in battery-backed systems.

Use Scenario: High-density telecom line cards integrate multiple FPGAs for packet processing, requiring scalable configuration memory across 4–8 devices.

IC Role / Device Role / Timing Role: AT17C128-10NI units are cascaded using CEO→CE interconnect, with TOCE ≤60 ns ensuring setup time compliance across backplane trace lengths.

Use Value: Pin-compatible PLCC/SOIC packaging allows layout reuse across density variants (64K/128K/256K), simplifying design migration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
AT17LV128-10NI	3.3V ±10% supply; slower max clock (8 MHz cascaded, 10 MHz standalone); higher AC delays (e.g., TCAC = 75–80 ns vs. 50–55 ns)	Required for 3.3V FPGA systems; not drop-in compatible due to voltage and timing differences	Select AT17LV128-10NI only when target FPGA operates at 3.3V and timing margins accommodate longer propagation delays.
Xilinx XC18V02	2 Mbit capacity; 3.3V-only; JTAG-programmable; no CEO output; different pinout and protocol (Xilinx proprietary)	Used in Xilinx-only designs with larger bitstreams; lacks native cascading support and requires JTAG infrastructure	Choose XC18V02 only for Xilinx-centric platforms needing >128 Kbit and accepting JTAG-based programming workflow.

Compared with AT17LV128-10NI and XC18V02, the AT17C128-10NI delivers deterministic 5V-compatible cascading, lower AC delays for timing-critical FPGA loads, and hardware write protection-making it optimal for industrial multi-FPGA systems operating from legacy 5V rails.

Availability

AT17C128-10NI is available at Aetrix Electronics and suitable for industrial PLCs, Xilinx SPARTAN FPGA boot systems, and Altera FLEX-based motor drives requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for AT17C128-10NI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel FPGA configuration EEPROMs, including manufacturing, documentation, and technical resources.

The AT17 Series was designed specifically for reliable, low-cost, in-system programmable configuration storage for SRAM-based FPGAs - targeting industrial, telecom, and embedded control applications where power-up repeatability and field update capability are essential.

FAQ

What is the maximum clock frequency supported by AT17C128-10NI in cascaded configuration?

The AT17C128-10NI supports a maximum input clock frequency of 8 MHz when used in cascaded mode, as specified in the AC Characteristics table for "AT17C128 When Cascading" under VCC = 5V ±10% industrial conditions. This timing ensures proper CEO assertion and handoff to the next device in the chain, with TOCK ≤60 ns guaranteeing setup compliance across temperature and voltage extremes. AT17C128-10NI must be operated within this limit to maintain deterministic configuration sequencing in multi-device systems.

Does AT17C128-10NI support in-system programming without removing it from the PCB?

Yes, AT17C128-10NI supports in-system programming via its 2-wire serial interface when SER_EN is pulled low. This mode requires only VCC-supplied voltage - no external programming voltage is needed. The device uses internal charge pumps to generate required programming voltages, allowing field updates of configuration bitstreams while mounted on the target board. AT17C128-10NI retains full functionality in both normal configuration mode (SER_EN = High) and programming mode (SER_EN = Low).

Can AT17C128-10NI be used with Xilinx SPARTAN FPGAs?

Yes, AT17C128-10NI is explicitly listed as compatible with Xilinx SPARTAN® FPGAs in the official Atmel documentation. It interfaces via master serial mode: FPGA CCLK drives AT17C128-10NI's CLK input, and AT17C128-10NI's DATA output connects to FPGA DIN. The AT17C128-10NI's programmable reset polarity and CEO output enable seamless integration with SPARTAN's PROG_B and configuration handoff requirements. AT17C128-10NI meets all timing and voltage specifications required for reliable SPARTAN bitstream loading.

What is the purpose of the CEO pin on AT17C128-10NI?

The CEO (Chip Enable Output) pin on AT17C128-10NI asserts low on the clock cycle immediately following the last bit read from memory, signaling completion of its configuration data stream. This output drives the CE input of the next AT17C/LV128 or AT17C/LV256 device in a daisy-chain, enabling automatic handoff without external control logic. Timing parameters like TOCE (≤60 ns) and TOCK (≤60 ns) ensure robust inter-device synchronization. AT17C128-10NI's CEO is essential for scaling configuration memory beyond 128 Kbit across multiple FPGAs.

Is AT17C128-10NI pin-compatible with other members of the AT17C/LV family?

Yes, AT17C128-10NI shares identical pinouts across all package variants (20J PLCC, 20S SOIC, 8P3 PDIP, 8S1 SOIC) and is pin-compatible with AT17C65-10NI and AT17C256-10NI in the same package type. This allows direct PCB footprint reuse when migrating between 64K, 128K, and 256K densities. However, AT17C128-10NI is not pin-compatible with AT17LV-series devices due to differing voltage and timing requirements, despite identical pin numbering and function mapping.

AT17C128-10NI Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

Programmable Type:: Serial EEPROM

Memory Size:: 128kb

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

AT17C128-10NI FAQ

1.How can I place an order for AT17C128-10NI through Aetrix?

Please submit a Request for Quotation (RFQ) for AT17C128-10NI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT17C128-10NI reliable?

The price and inventory of AT17C128-10NI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10NI is usually 5 days.

3.What payment methods are accepted for AT17C128-10NI?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10NI transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT17C128-10NI?

AT17C128-10NI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT17C128-10NI order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT17C128-10NI?

For technical support, including AT17C128-10NI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10NI requirements.

6.How does Aetrix verify that AT17C128-10NI is sourced from the original manufacturer or authorized distributors?

All AT17C128-10NI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10NI meets industry standards.

7.What is the process for return or replacement of AT17C128-10NI?

All AT17C128-10NI units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10NI, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT17C128-10NI part is unused and in its original packaging.

Return procedure for AT17C128-10NI:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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