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Microchip Technology AT17C128-10PC
- Part No.:
- AT17C128-10PC
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT17C128-10PC.pdf
- Description:
- IC SERIAL CONFIG PROM 128K 8DIP
- Quantity:
- Payment:
- Shipping:
Inventory:4,128
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Product details
Overview
AT17C128-10PC from Atmel is a 128K-bit (131,072 × 1) serial EEPROM FPGA configuration memory operating at 5V ± 5% with 10 MHz max clock frequency, programmable reset polarity, and cascading CEO output for multi-FPGA daisy-chain configuration in industrial embedded systems.
For engineers reviewing the AT17C128-10PC datasheet, AT17C128-10PC pinout, AT17C128-10PC application, or AT17C128-10PC equivalent, key selection criteria include 5V supply compatibility, CE/CEO cascade timing (TOCE = 55 ns), standby current (75 µA), programmable WP functionality, and PLCC/SOIC/PDIP package options.
Technical Context
The AT17C128-10PC implements a serial master-mode interface where FPGA CCLK drives CLK, DATA feeds DIN, and CEO enables cascaded EEPROMs. It supports in-system programming via 2-wire bus when SER_EN is low, with internal charge-pump voltage generation eliminating external programming voltages.
Its architecture includes a programmable reset polarity register, write-protect control via WP input during programming mode, and address counter synchronization via RESET/OE - critical for robust reconfiguration after system reset in industrial control FPGAs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 131,072 × 1-bit (128K-bit) nonvolatile storage for FPGA bitstream |
| Supply voltage | 5V ± 5% (commercial), supports industrial -40°C to +85°C operation |
| Max clock frequency | 10 MHz when cascading; ensures reliable timing margin for multi-device chains |
| Standby current | 75 µA at 5V - enables low-power hold during FPGA idle states |
| CEO propagation delay | TOCE = 55 ns (industrial/military) - defines minimum inter-device clock spacing in cascade |
| Reset polarity | Programmable active-high or active-low via EEPROM byte - eliminates need for external inverters |
| Write protection | Hardware WP input disables writes to lowest memory block when high during programming mode |
Pinout & Package
AT17C128-10PC is available in 8-pin PDIP (8P3), 8-lead SOIC (8S1), 20-lead PLCC (20J), and 20-lead SOIC (20S) packages. Pin functions are identical across all variants per Atmel documentation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DATA | I/O bidirectional open-collector | Drives FPGA DIN during configuration; supports 2-wire programming I/O |
| CLK | Input | Edge-triggered clock from FPGA CCLK; increments internal address/bit counters |
| RESET/OE | Input | Programmable reset/enable - resets address counters on active edge; controls output driver enable |
| CE | Input | Chip enable - disables counters and enters standby mode when high; selects device in cascade |
| GND | Power ground | Reference for all logic and analog functions; requires 0.2 µF decoupling capacitor |
| CEO | Output | Cascade enable output - goes low after last bit read to enable next EEPROM in chain |
| SER_EN | Input | Serial programming enable - must be high during FPGA configuration; low enables 2-wire ISP mode |
| VCC | Power supply | +5V ± 5% nominal supply; powers EEPROM core and I/O buffers |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | 2-wire serial interface with internal voltage generation - no external VPP required for field updates |
| Cascadable CEO output | Dedicated CEO pin with 55 ns TOCE delay - enables deterministic daisy-chain timing for >128K configurations |
| Programmable reset polarity | User-configurable active-high/low RESET/OE - eliminates board-level inverter components |
| Hardware write protection | WP input disables writes to first memory block when asserted - prevents accidental corruption of boot code |
| Low-power standby | 75 µA ICCS at 5V - reduces system power budget during FPGA initialization phases |
Applications
| Industrial PLC Configuration | FPGA-Based Motor Control |
|---|---|
Use Scenario: Configuring Xilinx XC4000 or Altera FLEX® FPGAs in programmable logic controllers deployed in factory automation environments. IC Role / Device Role / Timing Role: Serial configuration memory providing bitstream loading on power-up or reset, synchronized to FPGA CCLK with CEO-driven cascade for multi-axis motion control modules. Use Value: Guaranteed 10 MHz clock support and 55 ns CEO delay ensure deterministic startup timing across distributed I/O modules without firmware intervention. | Use Scenario: Storing safety-critical motor control algorithms in Lucent ORCA® FPGAs used in servo drive units with real-time position feedback loops. IC Role / Device Role / Timing Role: Nonvolatile configuration store with programmable reset polarity - maintains alignment between FPGA state machine and EEPROM address pointer after emergency stop-induced resets. Use Value: Active-low RESET/OE programming eliminates external reset conditioning circuitry, reducing BOM count and improving MTBF in harsh EMI environments. |
| Aerospace Avionics Bootloader | Telecom Baseband Processing |
Use Scenario: Loading configuration data into radiation-tolerant AT40K FPGAs within satellite communication subsystems requiring MIL-STD-883 qualified components. IC Role / Device Role / Timing Role: High-reliability configuration memory supporting -55°C to +125°C operation with 150 µA standby current at extended temperature range. Use Value: 5V ± 10% supply tolerance and 2000V ESD rating meet stringent aerospace power integrity and latch-up immunity requirements. | Use Scenario: Configuring SPARTAN® FPGAs in 3G/4G base station digital front-end modules requiring rapid field upgrades without hardware changes. IC Role / Device Role / Timing Role: Cascadable serial memory enabling modular bitstream partitioning across multiple FPGAs handling RF channelization and beamforming tasks. Use Value: CEO-driven daisy-chain allows single-point programming of multi-FPGA arrays via standard JTAG adapters, cutting test time by 60% versus individual device programming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10PC | 3.3V ± 10% supply; slower 8 MHz cascading clock; higher AC delays (e.g., TOCE = 55–60 ns) | Targeted for low-voltage FPGA platforms (e.g., Xilinx Spartan-3L); not suitable for 5V legacy designs | Select only if system uses 3.3V rails and FPGAs support LVCMOS I/O levels |
| XCR3256XL-10VQ100I | Integrated CPLD with onboard configuration memory; no external EEPROM needed; 100-pin VQFP package | Replaces discrete configuration memory + FPGA combo in space-constrained designs; requires CPLD-based architecture shift | Choose when redesigning for higher integration density and eliminating external memory bottlenecks |
Compared with AT17LV128-10PC, the AT17C128-10PC delivers 25% higher cascading clock speed (10 MHz vs. 8 MHz) and guaranteed 5V compatibility, while XCR3256XL-10VQ100I eliminates external memory entirely but mandates CPLD-based system rearchitecture.
Availability
AT17C128-10PC is available at Aetrix Electronics and suitable for industrial PLCs, aerospace avionics, and telecom baseband processing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT17C128-10PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation, now part of Microchip Technology, designed high-reliability nonvolatile memory and microcontroller solutions for industrial, automotive, and communications markets.
The AT17 Series was engineered specifically as FPGA configuration EEPROMs - delivering serial bitstream storage with cascade-ready timing, programmable reset, and industrial-grade voltage/temperature margins.
FAQ
What is the maximum clock frequency supported by AT17C128-10PC in cascaded configuration?
The AT17C128-10PC supports a maximum input clock frequency of 8 MHz when used in cascaded mode, as specified in its AC characteristics table for cascading operation. This timing constraint ensures reliable CEO assertion and inter-device handoff across daisy-chained configurations. The AT17C128-10PC must operate within this limit to maintain synchronization between cascaded devices during FPGA bitstream loading.
Does AT17C128-10PC require an external programming voltage for in-system programming?
No, the AT17C128-10PC does not require an external programming voltage. It features internal charge-pump circuitry that generates necessary programming voltages during 2-wire serial programming mode when SER_EN is pulled low. This eliminates the need for external VPP supplies and simplifies field reprogramming infrastructure for the AT17C128-10PC.
How does the programmable reset polarity feature work in AT17C128-10PC?
The AT17C128-10PC allows users to configure RESET/OE as either active-high or active-low via a dedicated EEPROM byte programmed using industry-standard algorithms. This setting determines whether a high or low signal on the RESET/OE pin resets the internal address counter - enabling direct connection to FPGA reset pins without external inverters. The AT17C128-10PC retains this setting across power cycles.
Can AT17C128-10PC be used with 3.3V FPGAs?
No, the AT17C128-10PC is a 5V-only device (5V ± 5% commercial, 5V ± 10% industrial/military) and is not compatible with 3.3V I/O standards. For 3.3V systems, the pin-compatible AT17LV128-10PC variant should be used instead. Interfacing the AT17C128-10PC directly with 3.3V FPGAs risks overvoltage damage to FPGA inputs and violates absolute maximum ratings.
What package options are available for AT17C128-10PC?
The AT17C128-10PC is offered in four package types: 8-pin PDIP (8P3), 8-lead SOIC (8S1), 20-lead PLCC (20J), and 20-lead SOIC (20S). All variants share identical pinouts and electrical specifications. The PLCC and SOIC packages provide surface-mount alternatives, while PDIP supports through-hole prototyping and legacy board designs using the AT17C128-10PC.
AT17C128-10PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT17C128-10PC FAQ
1.How can I place an order for AT17C128-10PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C128-10PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C128-10PC reliable?
The price and inventory of AT17C128-10PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10PC is usually 5 days.
3.What payment methods are accepted for AT17C128-10PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10PC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C128-10PC?
AT17C128-10PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C128-10PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C128-10PC?
For technical support, including AT17C128-10PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10PC requirements.
6.How does Aetrix verify that AT17C128-10PC is sourced from the original manufacturer or authorized distributors?
All AT17C128-10PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10PC meets industry standards.
7.What is the process for return or replacement of AT17C128-10PC?
All AT17C128-10PC units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C128-10PC part is unused and in its original packaging.
Return procedure for AT17C128-10PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17C128-10PC Tags
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AT17LV512A-10PU
Microchip Technology
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EPCQ4ASI8N
Intel
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AT17LV256-10PU
Microchip Technology
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AT17LV256-10NU
Microchip Technology
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EPCQ16ASI8N
Intel
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AT17LV010-10PU
Microchip Technology
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EPCQ32ASI8N
Intel
-
EPCQ64ASI16N
Intel
-
EPCQ128ASI16N
Intel
-
AT17LV512A-10JU
Microchip Technology
-
AT17LV512-10JU
Microchip Technology
-
AT17LV010-10JU
Microchip Technology
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