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Microchip Technology AT17C128-10PI
- Part No.:
- AT17C128-10PI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT17C128-10PI.pdf
- Description:
- IC SERIAL CONFIG PROM 128K 8DIP
- Quantity:
- Payment:
- Shipping:
Inventory:2,155
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Product details
Overview
AT17C128-10PI from Atmel is a 128K-bit (131,072 × 1) serial EEPROM FPGA configuration memory operating at 5V ±5% over -40°C to +85°C industrial temperature range. It features programmable reset polarity, cascading CEO output for multi-device chains, and compatibility with Xilinx XC3000/XC4000, Altera FLEX®, and Atmel AT40K/AT6000 FPGAs in Master Serial Mode.
For engineers reviewing the AT17C128-10PI datasheet, AT17C128-10PI pinout, AT17C128-10PI application, or AT17C128-10PI equivalent, key selection criteria include cascading support (CEO), 5V industrial-grade operation, write-protection via WP input, SER_EN-controlled 2-wire programming mode, and PLCC/SOIC/PDIP package flexibility.
Technical Context
The AT17C128-10PI implements a serial-access configuration memory architecture optimized for FPGA Master Serial Mode boot loading. Its internal address counter advances on CLK edges, synchronized to FPGA CCLK, with CEO assertion after final bit read to enable daisy-chained EEPROMs.
It supports two distinct hardware reset configurations: active-high RESET/OE (Condition 1) or active-low RESET/OE (Condition 2), both enabled by user-programmable EEPROM byte. SER_EN must be held high during FPGA configuration and pulled low only for in-system programming via 2-wire bus.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 131,072 × 1-bit (128K-bit) nonvolatile EEPROM storage for FPGA bitstream |
| Supply voltage | 5V ±5% - ensures compatibility with legacy 5V FPGA systems and industrial power rails |
| Operating temperature | -40°C to +85°C - qualified for industrial embedded control and communications equipment |
| Max clock frequency | 8 MHz when cascading - defines maximum CCLK rate for reliable multi-device chain timing |
| Standby current | 150 µA max - enables low-power system sleep modes without losing configuration state |
| Reset polarity | Programmable active-high or active-low - eliminates need for external inverters in FPGA reset interface |
| Write protection | WP input disables lowest memory block when high - prevents accidental corruption of critical boot code |
Pinout & Package
AT17C128-10PI is available in 20-lead PLCC (20J), 20-lead SOIC (20S), 8-pin PDIP (8P3), and 8-lead SOIC (8S1) packages. Pin functions are identical across all variants per Atmel's family pin-compatibility guarantee.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| DATA | I/O bidirectional | Three-state open-collector output driving FPGA DIN; used for serial data transfer during config and 2-wire programming |
| CLK | Input | Synchronizes internal address/bit counter to FPGA CCLK; determines configuration throughput rate |
| RESET/OE | Input | Programmable reset signal that clears address counter; also serves as output enable for DATA driver |
| CE | Input | Chip enable controlling standby mode entry (high = low-power); required for cascading chain sequencing |
| GND | Power | Ground reference for all logic and analog circuitry; requires 0.2 µF decoupling capacitor |
| CEO (A2) | Output | Chip Enable Output asserted low after last bit read; enables next EEPROM in cascade chain |
| SER_EN | Input | Serial enable - high during FPGA configuration, low to enter 2-wire ISP programming mode |
| VCC | Power | +5V supply pin; powers EEPROM core and I/O buffers; supports 5V ±5% tolerance |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Enables field firmware updates via 2-wire bus without removing device from PCB |
| Cascadable CEO output | Allows chaining multiple AT17C128-10PI devices to support larger FPGA configurations or multi-FPGA systems |
| Programmable reset polarity | Eliminates external level-shifting or inversion circuitry when interfacing with diverse FPGA reset architectures |
| Emulation of AT24CXXX EEPROMs | Permits reuse of existing serial EEPROM programming infrastructure and software tools |
| Low-power standby mode | Reduces system quiescent current to ≤150 µA while preserving stored configuration data |
Applications
| Industrial PLC Configuration | FPGA-Based Test Equipment |
|---|---|
Use Scenario: Configuring Xilinx XC4000-series FPGAs in programmable logic controllers deployed in factory automation environments with wide temperature swings. IC Role / Device Role / Timing Role: AT17C128-10PI serves as master serial configuration memory, delivering bitstream on power-up under FPGA CCLK control with CEO handoff to secondary EEPROMs if needed. Use Value: Industrial temperature rating (-40°C to +85°C) and 5V tolerance ensure reliable boot across unregulated plant-floor power supplies and thermal cycling. | Use Scenario: Storing multiple configuration images for reconfigurable digital signal processing cores in automated test equipment requiring rapid mode switching. IC Role / Device Role / Timing Role: AT17C128-10PI provides deterministic serial bitstream delivery synchronized to FPGA CCLK, with SER_EN enabling in-field image updates without board removal. Use Value: Cascading CEO support allows expansion beyond 128K-bit capacity using identical AT17C128-10PI devices, simplifying BOM management. |
| Avionics Data Acquisition | Communications Baseband Processing |
Use Scenario: Booting radiation-tolerant Altera FLEX FPGAs in airborne data acquisition units where configuration integrity and restart reliability are mission-critical. IC Role / Device Role / Timing Role: AT17C128-10PI acts as fault-resilient configuration source, with programmable RESET/OE polarity ensuring correct reset alignment with avionics power-on sequencing. Use Value: Write-protection via WP input prevents inadvertent overwrite of validated flight-critical bitstreams during maintenance operations. | Use Scenario: Loading baseband processing algorithms into Xilinx SPARTAN FPGAs within cellular base station remote radio units operating in outdoor enclosures. IC Role / Device Role / Timing Role: AT17C128-10PI delivers configuration data in Master Serial Mode, with CEO output enabling dual-device cascading for future algorithm upgrades without hardware redesign. Use Value: Low standby current (≤150 µA) minimizes thermal load in thermally constrained RF enclosures while retaining full configuration retention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10PI | 3.3V-only operation (3.0–3.6V), slower max clock (10 MHz vs. 8 MHz cascaded), lower standby current (100 µA) | Requires 3.3V FPGA ecosystem; not compatible with 5V-only designs or mixed-voltage boards | Select when migrating to 3.3V FPGA platforms and lower power is prioritized over voltage compatibility |
| XCR3064XL-10VQG44C | Integrated CPLD with onboard configuration memory; no external EEPROM needed; 3.3V operation only | Replaces discrete configuration memory + FPGA with single-chip solution; limited to Xilinx CoolRunner-II family | Select only for new designs targeting Xilinx CPLDs where footprint reduction outweighs flexibility of standalone EEPROM |
Compared with AT17LV128-10PI, the AT17C128-10PI offers essential 5V compatibility for legacy industrial systems, while the XCR3064XL-10VQG44C eliminates external memory but locks design to a specific CPLD family and voltage domain.
Availability
AT17C128-10PI is available at Aetrix Electronics and suitable for industrial PLCs, FPGA-based test equipment, avionics data acquisition, and communications baseband processing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for AT17C128-10PI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions for industrial, automotive, and communications markets.
The AT17 Series was designed specifically to provide cost-effective, pin-compatible serial configuration memory for SRAM-based FPGAs including Xilinx, Altera, and Atmel families, emphasizing ease of integration and in-system programmability.
FAQ
What is the primary function of the AT17C128-10PI in an FPGA system?
The AT17C128-10PI serves as a dedicated serial configuration memory that stores and delivers the bitstream required to initialize SRAM-based FPGAs such as Xilinx XC4000 or Altera FLEX devices in Master Serial Mode. During power-up or reset, the FPGA drives CLK and reads configuration data from AT17C128-10PI's DATA pin, with CEO enabling cascaded devices when needed.
Does the AT17C128-10PI support in-system programming, and how is it enabled?
Yes, the AT17C128-10PI supports in-system programming (ISP) via a 2-wire serial interface. This mode is activated by pulling the SER_EN pin low, which disables normal configuration operation and enables direct EEPROM memory writes using industry-standard programmers or Atmel's ATDH2200E kit - all at nominal VCC without external programming voltages.
How does the CEO pin function in a cascaded AT17C128-10PI configuration?
In a cascade chain, the CEO (Chip Enable Output) pin of one AT17C128-10PI asserts low on the clock cycle immediately following its final bit read. This low signal enables the CE input of the next AT17C128-10PI in the chain, allowing seamless handoff of configuration data flow without FPGA intervention or additional control logic.
Can the AT17C128-10PI be used with both 5V and 3.3V FPGAs?
No - the AT17C128-10PI is a 5V-only device specified for VCC = 4.5V to 5.5V across industrial temperature range. For 3.3V FPGA systems, the pin-compatible AT17LV128-10PI variant must be used, as mixing voltage domains risks damage or unreliable operation due to incompatible logic thresholds and internal charge pump requirements.
What packaging options are available for the AT17C128-10PI, and are they pin-compatible?
The AT17C128-10PI is offered in four packages: 20-lead PLCC (20J), 20-lead SOIC (20S), 8-pin PDIP (8P3), and 8-lead SOIC (8S1). All share identical pinouts and electrical characteristics per Atmel's documentation, enabling drop-in substitution based on board layout, thermal, or mechanical constraints without redesign.
AT17C128-10PI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT17C128-10PI FAQ
1.How can I place an order for AT17C128-10PI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C128-10PI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C128-10PI reliable?
The price and inventory of AT17C128-10PI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10PI is usually 5 days.
3.What payment methods are accepted for AT17C128-10PI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10PI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C128-10PI?
AT17C128-10PI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C128-10PI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C128-10PI?
For technical support, including AT17C128-10PI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10PI requirements.
6.How does Aetrix verify that AT17C128-10PI is sourced from the original manufacturer or authorized distributors?
All AT17C128-10PI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10PI meets industry standards.
7.What is the process for return or replacement of AT17C128-10PI?
All AT17C128-10PI units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10PI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C128-10PI part is unused and in its original packaging.
Return procedure for AT17C128-10PI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17C128-10PI Tags
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