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Microchip Technology AT17C128-10SC
- Part No.:
- AT17C128-10SC
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT17C128-10SC.pdf
- Description:
- IC EEPROM FPGA 128KB 20-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,786
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Product details
Overview
AT17C128-10SC from Microchip Technology (formerly Atmel) is a 128K-bit (131,072 × 1) serial EEPROM FPGA configuration memory with 5V ±5% supply operation, programmable reset polarity, and cascading CEO output for multi-FPGA daisy-chain loading. It interfaces directly with Xilinx XC4000/SPARTAN®, Altera FLEX®, and Atmel AT40K/AT6000 FPGAs in Master Serial Mode.
For engineers reviewing the AT17C128-10SC datasheet, AT17C128-10SC pinout, AT17C128-10SC application, or AT17C128-10SC equivalent, this device is selected for reliable, in-system programmable configuration storage in industrial-grade FPGA systems requiring stable timing alignment, low-power standby (<75 µA), and write-protection via WP input.
Technical Context
The AT17C128-10SC operates in Master Serial Mode, where the FPGA's CCLK drives the EEPROM's CLK pin to synchronize bit-serial readout of configuration data to DIN. Its CEO output enables cascaded chaining with other AT17C/LV128 or AT17C/LV256 devices, asserting low after final bit read to enable the next device's DATA line.
It supports two hardware reset configurations: active-High RESET/OE (Condition 1) or active-Low RESET/OE (Condition 2), both programmable via internal EEPROM byte. SER_EN must be held high during FPGA configuration and pulled low only during 2-wire ISP programming at VCC = 5V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 131,072 × 1-bit (128K-bit) nonvolatile configuration storage |
| Supply voltage | 5V ±5% (Commercial), 5V ±10% (Industrial/Military); no external programming voltage required |
| Max clock frequency | 12.5 MHz for standalone operation; 8 MHz when cascading |
| Standby current | <75 µA at 5.0V (Commercial), enabling low-power system sleep states |
| Reset polarity | Programmable active-High or active-Low via internal EEPROM byte |
| Write protection | Hardware WP input disables writes to lowest memory block when high (active in 2-wire mode) |
| Operating temperature | -40°C to +85°C (Industrial grade, per -10SI/-10SC suffix) |
Pinout & Package
AT17C128-10SC is packaged in a 20-lead SOIC (20S) with 0.300" body width, JEDEC-compliant gull-wing leads, and 1.27 mm pitch. Pin 1 is marked by a beveled corner or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | DATA | Bi-directional open-collector I/O for configuration data output and 2-wire programming data |
| 2 | CLK | Input clock synchronized to FPGA CCLK; increments internal address/bit counter on rising edge |
| 3 | (WP) RESET/OE | Programmable dual-function input: active-High reset or active-Low output enable; also serves as write-protect control in programming mode |
| 4 | CE | Chip Enable input; high forces low-power standby mode and disables counters |
| 5 | GND | Ground reference; requires 0.2 µF decoupling capacitor to VCC |
| 6 | CEO (A2) | Chip Enable Output / Device select input; outputs low after last bit read to cascade next device; A2 used for device selection during 2-wire programming |
| 7 | SER_EN | Serial Enable input; must be high during FPGA configuration; low enables 2-wire ISP mode |
| 8 | VCC | +5V power supply pin; supports 5V ±5% (Commercial) and 5V ±10% (Industrial/Military) |
| 9–10, 12–13, 15–16, 18–19 | NC | No-connect pins; internally unconnected and must remain floating or tied to GND/VCC per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | 2-wire serial interface (SER_EN low) enables field reprogramming without socket removal |
| Cascadable CEO output | Enables daisy-chain configuration of multiple FPGAs using single CCLK source and automatic handoff between AT17C128-10SC devices |
| Programmable reset polarity | Eliminates need for external inverters by allowing user to configure RESET/OE as active-High or active-Low via EEPROM byte |
| FPGA compatibility | Native support for Xilinx XC4000/SPARTAN®, Altera FLEX®, Lucent ORCA®, and Atmel AT40K/AT6000 families in Master Serial Mode |
| Low-power standby | Consumes <75 µA at 5V, reducing system-level quiescent power during FPGA initialization or idle states |
Applications
| Industrial PLC Configuration Storage | Xilinx SPARTAN FPGA Boot Memory |
|---|---|
|
Use Scenario: Storing bitstream configuration for Xilinx SPARTAN-3 FPGAs in factory automation controllers requiring cold-start reliability and long-term data retention. IC Role / Device Role / Timing Role: Primary serial configuration memory delivering bitstream on power-up via Master Serial Mode; synchronized to FPGA CCLK at up to 12.5 MHz. Use Value: Ensures deterministic FPGA startup within 100 ms, with 100-year data retention and immunity to power glitches due to EEPROM nonvolatility. |
Use Scenario: Loading configuration data into Xilinx SPARTAN-2 FPGAs used in motor drive gate control modules operating across -40°C to +85°C ambient. IC Role / Device Role / Timing Role: Industrial-grade configuration EEPROM providing CE-gated standby mode and programmable reset polarity to match FPGA reset sequencing. Use Value: Eliminates external reset synchronization logic and reduces BOM count by integrating write-protection (WP) and cascading (CEO) in one 20-pin SOIC package. |
| Altera FLEX 10K Daisy-Chain Systems | Atmel AT40K FPGA Configuration |
|
Use Scenario: Cascading three AT17C128-10SC devices to configure a multi-FPGA system using Altera FLEX 10KA devices in telecom baseband processing. IC Role / Device Role / Timing Role: Mid-chain configuration EEPROM with CEO-driven handoff; each device asserts CEO low after final bit to enable next DATA line. Use Value: Enables scalable configuration memory expansion beyond 128K-bit without FPGA firmware changes or additional clock routing. |
Use Scenario: Single-chip configuration memory for Atmel AT40K10 FPGAs in medical imaging subsystems requiring ESD-hardened, MIL-qualified components. IC Role / Device Role / Timing Role: Directly compatible AT17-series configurator supporting AT40K Master Serial Mode with SER_EN-controlled ISP capability. Use Value: Guarantees bit-accurate configuration delivery under ESD stress (2000V HBM) and maintains synchronization during brown-out events via programmable reset polarity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10SC | 3.3V ±10% operation; lower max clock (10 MHz standalone, 8 MHz cascaded); higher AC delays (e.g., TCAC = 75–80 ns vs. 50–55 ns) | Required for 3.3V FPGA systems; not drop-in compatible with 5V designs due to voltage and timing mismatch | Select AT17LV128-10SC only when host FPGA uses 3.3V I/O banks and timing budget allows slower clocking. |
| AT17C256-10SC | 256K-bit capacity (2× memory); identical 5V supply, pinout, and AC specs except FMAX = 12.5 MHz (standalone) and 10 MHz (cascaded) | Used when single-FPGA bitstream exceeds 128K-bit; occupies same 20S footprint but requires updated programming file | Choose AT17C256-10SC if future FPGA upgrades demand larger configuration space while retaining same PCB layout and power design. |
Compared with AT17LV128-10SC and AT17C256-10SC, the AT17C128-10SC delivers optimal balance of 5V compatibility, industrial temperature range, and 128K-bit capacity-making it the standard choice for legacy and cost-sensitive FPGA systems where voltage and memory size are fixed constraints.
Availability
AT17C128-10SC is available at Aetrix Electronics and suitable for industrial PLCs, Xilinx SPARTAN-based motor drives, and Altera FLEX daisy-chain systems requiring stable component supply, long-lifecycle support, and guaranteed traceable sourcing.
Supply support for AT17C128-10SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full product continuity, documentation, and support for the AT17 series. Atmel pioneered FPGA configuration memory solutions with industry-standard serial interfaces.
The AT17 series was designed specifically for reliable, low-pin-count configuration storage in SRAM-based FPGAs-including Xilinx, Altera, and Atmel families-emphasizing ease of integration, in-system programmability, and industrial-grade robustness.
FAQ
What is the operating voltage range for AT17C128-10SC?
The AT17C128-10SC operates at 5V ±5% for Commercial grade and 5V ±10% for Industrial and Military grades. It draws power solely from VCC; no auxiliary voltages or programming super-voltages are required. The device generates internal programming voltages during 2-wire ISP mode, ensuring compatibility with standard 5V system rails. This makes AT17C128-10SC suitable for legacy 5V FPGA platforms without level-shifting circuitry.
How does the CEO pin function in a cascaded configuration with AT17C128-10SC?
In cascaded setups, the CEO pin of AT17C128-10SC goes low on the clock cycle immediately following the last configuration bit read, disabling its DATA driver and enabling the CE input of the next AT17C/LV128 or AT17C/LV256 device. This handoff is fully hardware-synchronized to CCLK and requires no FPGA firmware intervention. AT17C128-10SC supports mid-chain placement but cannot be followed by an AT17C65 due to missing CEO functionality in the smaller variant.
Can AT17C128-10SC be programmed in-circuit without removing it from the PCB?
Yes, AT17C128-10SC supports in-system programming (ISP) via its 2-wire serial interface when SER_EN is pulled low. Programming occurs at the nominal VCC supply (5V), with all required voltages generated internally-no external VPP or special programmers needed. Industry-standard programmers and Atmel's ATDH2200E kit are compatible. The AT17C128-10SC retains full read/write functionality while mounted, enabling field updates of FPGA configuration bitstreams.
What is the purpose of the (WP) RESET/OE pin on AT17C128-10SC?
The pin labeled (WP) RESET/OE on AT17C128-10SC serves three distinct roles: as active-High RESET input (to reset internal address counters), as active-Low OE input (to enable DATA output), and as Write Protect (WP) control during 2-wire programming (high = protect lowest memory block). Its polarity is user-programmable via an internal EEPROM byte, eliminating external inverters and simplifying reset synchronization with diverse FPGA families.
Which FPGA families are explicitly supported by AT17C128-10SC according to official documentation?
AT17C128-10SC is documented as compatible with Atmel AT6000 and AT40K FPGAs, Altera FLEX® devices, Lucent ORCA® FPGAs, Xilinx XC3000/XC4000/XC5200/SPARTAN® families, and Motorola MPA1000 FPGAs. This support is validated through Master Serial Mode timing alignment, pin mapping (DATA→DIN, CLK→CCLK), and application notes including "AT6000 Series Configuration" and "AT40K Series Configuration." No software abstraction layer is required-hardware connection suffices.
AT17C128-10SC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
AT17C128-10SC FAQ
1.How can I place an order for AT17C128-10SC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C128-10SC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C128-10SC reliable?
The price and inventory of AT17C128-10SC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10SC is usually 5 days.
3.What payment methods are accepted for AT17C128-10SC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10SC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C128-10SC?
AT17C128-10SC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C128-10SC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C128-10SC?
For technical support, including AT17C128-10SC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10SC requirements.
6.How does Aetrix verify that AT17C128-10SC is sourced from the original manufacturer or authorized distributors?
All AT17C128-10SC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10SC meets industry standards.
7.What is the process for return or replacement of AT17C128-10SC?
All AT17C128-10SC units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10SC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C128-10SC part is unused and in its original packaging.
Return procedure for AT17C128-10SC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17C128-10SC Tags
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AT17LV512A-10PU
Microchip Technology
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EPCQ4ASI8N
Intel
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AT17LV256-10PU
Microchip Technology
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AT17LV256-10NU
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EPCQ16ASI8N
Intel
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AT17LV010-10PU
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EPCQ32ASI8N
Intel
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EPCQ64ASI16N
Intel
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EPCQ128ASI16N
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AT17LV512A-10JU
Microchip Technology
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AT17LV512-10JU
Microchip Technology
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AT17LV010-10JU
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