My Inquiry
My Account
Microchip Technology AT17C128-10SI
- Part No.:
- AT17C128-10SI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT17C128-10SI.pdf
- Description:
- IC EEPROM FPGA 128KB 20-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:4,737
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT17C128-10SI from Microchip Technology (formerly Atmel) is a 128 Kbit (131,072 × 1-bit) serial EEPROM FPGA configuration memory with 5V ±10% industrial supply support, programmable reset polarity, and cascading CEO output for multi-FPGA daisy-chain loading. It interfaces directly with Xilinx XC4000/SPARTAN®, Altera FLEX®, and Atmel AT40K/AT6000 FPGAs in Master Serial Mode.
For engineers reviewing the AT17C128-10SI datasheet, AT17C128-10SI pinout, AT17C128-10SI application, or AT17C128-10SI equivalent, key selection criteria include industrial temperature range (-40°C to +85°C), 20-lead PLCC package compatibility, cascading capability via CEO, 8 MHz max clock frequency in cascade mode, and in-system programmability via 2-wire bus.
Technical Context
The AT17C128-10SI operates as a dedicated serial configuration memory for SRAM-based FPGAs, using a synchronous serial interface driven by the FPGA's CCLK signal. Its internal address counter auto-increments on each CLK edge, delivering configuration bits sequentially from DATA pin.
It supports two distinct hardware configurations: Condition 1 (FPGA CON drives both CE and RESET/OE, requiring active-High reset polarity) and Condition 2 (RESET/OE tied to FPGA RESET pin, enabling active-Low reset and robust reconfiguration recovery). SER_EN must be held High during FPGA boot and pulled Low only for 2-wire ISP programming.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 131,072 × 1-bit (128 Kbit) nonvolatile EEPROM storage for full FPGA bitstream |
| Supply voltage | 5V ±10% - supports industrial-grade operation from -40°C to +85°C |
| Max clock frequency | 8 MHz in cascaded mode - limits configuration speed when chaining multiple devices |
| Standby current | 150 µA max at 5V - enables low-power system suspend during idle periods |
| Reset polarity | Programmable active-High or active-Low - eliminates need for external inverters |
| Cascade support | CEO output asserts Low after final bit read - enables automatic handoff to next EEPROM in chain |
| Write protection | Hardware WP input disables write to lowest memory block when CE is Low - prevents accidental corruption of critical boot data |
Pinout & Package
AT17C128-10SI is supplied in a 20-lead Plastic J-Leaded Chip Carrier (PLCC) package, pin-compatible across the AT17C/LV65/128/256 family. The PLCC footprint supports socketed prototyping and high-reliability industrial mounting.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | DATA | Three-state bidirectional I/O - delivers configuration bits to FPGA DIN; open-collector during programming |
| 2 | CLK | Input - synchronizes internal address counter and bit delivery to FPGA CCLK |
| 3 | RESET/OE | Input - resets address/bit counters when active; polarity programmable (High or Low) |
| 4 | CE | Input - enables device and data output when Low; forces standby mode when High |
| 5 | GND | Ground reference - requires 0.2 µF decoupling capacitor to VCC |
| 6 | CEO | Output - goes Low one cycle after last bit read, enabling next cascaded EEPROM |
| 7 | SER_EN | Input - must be High during FPGA configuration; Low enables 2-wire ISP programming mode |
| 8 | VCC | Power supply - accepts 5V ±10% for industrial operation |
| 9–20 | NC | No-connect - internally unconnected; must remain floating or grounded per layout guidelines |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | 2-wire serial interface (SER_EN + DATA/CLK) enables field updates without removing device from PCB |
| Cascadable architecture | CEO output automates daisy-chain handoff between AT17C128-10SI units - supports >128 Kbit total configuration memory |
| FPGA vendor compatibility | Native timing and signaling match Xilinx XC4000/SPARTAN®, Altera FLEX®, Lucent ORCA®, and Atmel AT40K/AT6000 families |
| Emulation mode | Behaves as AT24CXXX serial EEPROM - allows reuse of existing EEPROM programming infrastructure |
| Low-power standby | 150 µA max ICCS at 5V - reduces system power budget during FPGA initialization or sleep states |
Applications
| Industrial PLC Configuration | Xilinx SPARTAN FPGA Boot |
|---|---|
|
Use Scenario: Storing and loading FPGA configuration bitstreams in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Dedicated serial configuration memory providing deterministic, repeatable boot sequence synchronized to FPGA CCLK. Use Value: Industrial temperature rating (-40°C to +85°C) and 150 µA standby current ensure reliable operation under thermal stress and extended uptime requirements. |
Use Scenario: Initializing Xilinx SPARTAN-series FPGAs at power-up in embedded vision systems with strict boot-time constraints. IC Role / Device Role / Timing Role: Master Serial Mode configuration source delivering bitstream via DATA pin, timed by FPGA-generated CLK. Use Value: 8 MHz max cascade clock frequency and CEO handoff enable scalable bitstream delivery for multi-FPGA vision pipelines. |
| Altera FLEX® Daisy Chain | Atmel AT40K Reconfiguration |
|
Use Scenario: Cascading multiple AT17C128-10SI devices to configure large Altera FLEX® FPGA arrays exceeding 128 Kbit capacity. IC Role / Device Role / Timing Role: First-stage configuration memory asserting CEO to enable second-stage AT17C128-10SI upon completion. Use Value: Hardware CEO signaling eliminates need for FPGA GPIO control or firmware coordination between EEPROMs. |
Use Scenario: Field-updating configuration data for Atmel AT40K FPGAs in deployed telecom baseband modules. IC Role / Device Role / Timing Role: In-system programmable configuration store supporting 2-wire ISP without board removal or JTAG dependency. Use Value: SER_EN-controlled programming mode allows safe field updates while preserving existing FPGA functionality during partial reconfiguration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10SI | 3.3V ±10% supply, 10 MHz max clock (non-cascade), higher AC delays (e.g., TCAC = 75–80 ns) | Targets 3.3V FPGA platforms; not drop-in compatible due to voltage and timing mismatch | Select only for new 3.3V designs where lower power and reduced EMI are prioritized over legacy 5V interoperability |
| XCR3256XL-10VQG100I | Integrated CPLD with on-chip configuration memory - no external EEPROM required | Eliminates discrete configuration memory but fixes FPGA type and limits upgrade flexibility | Choose for cost-sensitive, single-FPGA applications where design lock-in and reduced BOM count outweigh configurability needs |
Compared with AT17LV128-10SI, the AT17C128-10SI provides guaranteed 5V industrial operation and cascade-tuned timing (8 MHz CEO handoff), while XCR3256XL-10VQG100I replaces external configuration entirely but sacrifices FPGA vendor flexibility and field reprogrammability.
Availability
AT17C128-10SI is available at Aetrix Electronics and suitable for industrial PLCs, Xilinx SPARTAN FPGA boot systems, Altera FLEX® daisy-chain deployments, and Atmel AT40K reconfiguration applications requiring stable component supply across extended product lifecycles.
Supply support for AT17C128-10SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full support for legacy Atmel FPGA configuration products, including datasheets, programming tools, and long-term supply assurance.
The AT17C series was designed specifically for reliable, pin-compatible configuration memory in SRAM-based FPGA systems - emphasizing industrial temperature resilience, cascade scalability, and in-system update capability.
FAQ
What is the operating temperature range for AT17C128-10SI?
The AT17C128-10SI is rated for industrial operation from -40°C to +85°C. This range is confirmed in the "Operating Conditions" table of the official datasheet and applies to all electrical specifications including standby current (150 µA max) and AC timing (e.g., 8 MHz cascade clock). The "-10SI" suffix explicitly denotes the industrial temperature grade and 20-lead PLCC package.
Does AT17C128-10SI support cascading with other AT17C devices?
Yes, AT17C128-10SI supports hardware cascading exclusively with other AT17C128 or AT17C256 devices via its CEO output. When the last configuration bit is read, CEO asserts Low to enable the CE input of the next cascaded AT17C128-10SI. AT17C65 cannot be used mid-chain - it supports only standalone or end-of-chain placement.
Can AT17C128-10SI be programmed in-circuit without removing it from the board?
Yes, AT17C128-10SI supports in-system programming (ISP) via its 2-wire serial interface. Bringing SER_EN Low activates ISP mode, allowing reprogramming of configuration data using standard industry programmers or Atmel's ATDH2200E kit - all while the device remains soldered to the PCB and powered at 5V.
What FPGA families is AT17C128-10SI officially compatible with?
AT17C128-10SI is documented as compatible with Xilinx XC3000/XC4000/XC5200/SPARTAN®, Altera FLEX®, Lucent ORCA®, Motorola MPA1000, and Atmel AT40K/AT6000 FPGAs. Compatibility is verified through timing alignment with Master Serial Mode, pin mapping (DATA→DIN, CLK→CCLK), and functional validation in Atmel application notes.
Is the reset polarity of AT17C128-10SI fixed or configurable?
The reset polarity of AT17C128-10SI is fully programmable - it can be set to active-High or active-Low via a dedicated EEPROM byte during programming. This eliminates external inverter components and supports both Condition 1 (CON-driven CE+RESET/OE) and Condition 2 (separate RESET pin) FPGA interface topologies described in the datasheet.
AT17C128-10SI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
AT17C128-10SI FAQ
1.How can I place an order for AT17C128-10SI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17C128-10SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17C128-10SI reliable?
The price and inventory of AT17C128-10SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17C128-10SI is usually 5 days.
3.What payment methods are accepted for AT17C128-10SI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17C128-10SI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17C128-10SI?
AT17C128-10SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17C128-10SI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17C128-10SI?
For technical support, including AT17C128-10SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17C128-10SI requirements.
6.How does Aetrix verify that AT17C128-10SI is sourced from the original manufacturer or authorized distributors?
All AT17C128-10SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17C128-10SI meets industry standards.
7.What is the process for return or replacement of AT17C128-10SI?
All AT17C128-10SI units undergo pre-shipment inspection (PSI). If there is an issue with AT17C128-10SI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17C128-10SI part is unused and in its original packaging.
Return procedure for AT17C128-10SI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17C128-10SI Tags
-
AT17LV512A-10PU
Microchip Technology
-
EPCQ4ASI8N
Intel
-
AT17LV256-10PU
Microchip Technology
-
AT17LV256-10NU
Microchip Technology
-
EPCQ16ASI8N
Intel
-
AT17LV010-10PU
Microchip Technology
-
EPCQ32ASI8N
Intel
-
EPCQ64ASI16N
Intel
-
EPCQ128ASI16N
Intel
-
AT17LV512A-10JU
Microchip Technology
-
AT17LV512-10JU
Microchip Technology
-
AT17LV010-10JU
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
