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Microchip Technology AT17LV128-10JI
- Part No.:
- AT17LV128-10JI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 20-LCC (J-Lead)
- Datasheet:
-
AT17LV128-10JI.pdf
- Description:
- IC EEPROM FPGA 128KB 20-PLCC
- Quantity:
- Payment:
- Shipping:
Inventory:3,389
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Product details
Overview
AT17LV128-10JI from Atmel is a 128-Kbit (131,072 × 1-bit) serial EEPROM FPGA configuration memory supporting both 3.3V and 5.0V operation, featuring in-system programmability via two-wire bus, programmable reset polarity, and cascading capability via CEO output for multi-FPGA systems. It targets industrial-grade FPGA configuration in SRAM-based logic designs.
For engineers reviewing the AT17LV128-10JI datasheet, AT17LV128-10JI pinout, AT17LV128-10JI application, or AT17LV128-10JI equivalent, key selection criteria include industrial temperature range (−40°C to +85°C), 20-lead PLCC package compatibility, low-power standby current (100 µA at 3.3V), EEPROM endurance (100,000 write cycles), and FPGA master serial mode timing compliance.
Technical Context
The AT17LV128-10JI operates in FPGA master serial configuration mode, interfacing directly with CCLK, DIN, CE, and RESET/OE signals of SRAM FPGAs without external controllers. Its internal address counter auto-resets on power-up and supports daisy-chain cascading via CEO output to enable larger configuration bitstreams.
It implements dual-voltage support through internal regulation and uses a CMOS EEPROM process enabling 90-year data retention at 85°C. Programming occurs in two-wire serial mode when SER_EN is low, with WP input protecting the lowest memory block during write operations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (131,072 × 1-bit) - sufficient for mid-density Xilinx XC4000 or Altera FLEX 10K FPGA configurations |
| Supply voltage | 3.3 V ±10% or 5.0 V ±5% (commercial) / ±10% (industrial) - enables direct integration into mixed-voltage FPGA systems |
| Operating temperature | −40°C to +85°C - qualified for industrial embedded control and communications equipment |
| Standby current | 100 µA at 3.3 V (industrial) - reduces system-level power budget during FPGA configuration idle states |
| Write endurance | 100,000 write cycles - supports field firmware updates and reconfiguration in deployed systems |
| Data retention | 90 years at 85°C - ensures long-term reliability in unattended industrial deployments |
| Max clock frequency | 10 MHz at 3.3 V (industrial), 12.5 MHz at 5 V (commercial) - meets timing requirements for fast FPGA startup |
Pinout & Package
AT17LV128-10JI is packaged in a 20-lead PLCC (Plastic Leaded Chip Carrier) with 1.27 mm lead pitch, JEDEC MS-018 compliant, footprint dimensions 9.78 mm × 9.78 mm × 3.56 mm (max height), and lead coplanarity ≤0.102 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20 | NC / GND / VCC / DATA / CLK / RESET/OE / CE / SER_EN / CEO / WP1 | Pins 1–20 follow JEDEC 20J pinout: Pin 1 = CLK, Pin 2 = WP1, Pin 3 = NC, Pin 4 = RESET/OE, Pin 5 = WP2, Pin 6 = NC, Pin 7 = CE, Pin 8 = NC, Pin 9 = SER_EN, Pin 10 = NC, Pin 11 = NC, Pin 12 = GND, Pin 13 = NC, Pin 14 = CEO, Pin 15 = NC, Pin 16 = NC, Pin 17 = NC, Pin 18 = NC, Pin 19 = DATA, Pin 20 = VCC - exact mapping per Figure 2-4 and Table 4-1 |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability (ISP) | Enables field firmware updates via two-wire serial interface without removing device from PCB |
| Cascadable CEO output | Allows daisy-chaining multiple AT17LV devices to extend total configuration memory beyond 128 Kbit |
| Programmable reset polarity | Supports both active-low RESET and active-high OE modes to match diverse FPGA control signal conventions |
| Low-power standby mode | Draws only 100 µA at 3.3 V (industrial), reducing quiescent power in always-on systems |
| Green RoHS-compliant options | Available in Pb/halide-free packages (e.g., AT17LV128-10JU) meeting environmental compliance mandates |
Applications
| Industrial PLC Configuration | Xilinx XC4000 FPGA Boot |
|---|---|
Use Scenario: Configuring SRAM-based FPGAs in programmable logic controllers operating continuously in factory environments. IC Role / Device Role / Timing Role: Serial configuration memory providing deterministic bitstream loading at power-up or on command via FPGA master serial interface. Use Value: 90-year data retention at 85°C ensures reliable boot across 10+ year product lifecycles without reprogramming. | Use Scenario: Loading configuration bitstreams into Xilinx XC4000-series FPGAs used in high-reliability test equipment. IC Role / Device Role / Timing Role: Dedicated EEPROM acting as nonvolatile storage for FPGA configuration data, synchronized to CCLK with TOE ≤55 ns (industrial). Use Value: 10 MHz max clock frequency at 3.3 V enables sub-100 ms FPGA startup time, critical for rapid instrument initialization. |
| Altera FLEX 10K Daisy Chain | Multi-FPGA Telecommunications Board |
Use Scenario: Cascading multiple AT17LV128-10JI devices to configure large Altera FLEX 10K FPGA arrays in baseband processing modules. IC Role / Device Role / Timing Role: First-stage configurator driving CEO to enable second-stage AT17LV device, with TOCE ≤60 ns ensuring clean inter-device handoff. Use Value: CEO-driven cascading eliminates need for external logic or microcontroller coordination, simplifying board design. | Use Scenario: Providing independent configuration storage for three SRAM FPGAs on a single telecom line card requiring hot-swap capability. IC Role / Device Role / Timing Role: Industrial-grade configuration EEPROM supporting simultaneous or staggered FPGA boot sequences under −40°C to +85°C ambient conditions. Use Value: 20-lead PLCC package allows manual rework and socketing for field serviceability, unlike fine-pitch TQFP alternatives. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Xilinx XC18V02 | 2-Mbit capacity, 3.3 V only, no 5 V support, different pinout (20-pin SOIC), no CEO cascading | Targeted for Xilinx-only systems; lacks dual-voltage flexibility and daisy-chain capability | Select when higher density is required and 5 V compatibility is unnecessary |
| Microchip 25LC1024 | 1-Mbit SPI EEPROM, no built-in FPGA configuration protocol, requires external controller for bitstream loading | Suitable for custom configuration loaders but not plug-and-play FPGA master serial mode | Choose only if implementing custom configuration logic or needing SPI interface flexibility |
Compared with XC18V02 and 25LC1024, AT17LV128-10JI delivers native FPGA master serial support, dual-voltage operation, and hardware CEO cascading-enabling simpler, more robust, and lower-BOM-cost FPGA boot architectures in industrial environments.
Availability
AT17LV128-10JI is available at Aetrix Electronics and suitable for industrial automation, telecommunications infrastructure, and embedded FPGA-based instrumentation requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for AT17LV128-10JI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions for industrial, automotive, and communications markets.
The AT17LV series was designed specifically as serial configuration EEPROMs for SRAM-based FPGAs, emphasizing ease of integration, industrial reliability, and support for master serial boot protocols used by Xilinx, Altera, and Atmel FPGA families.
FAQ
What is the memory organization of the AT17LV128-10JI?
The AT17LV128-10JI provides 131,072 × 1-bit serial EEPROM memory, organized as a single linear array optimized for sequential FPGA configuration bitstream loading. It does not support byte-addressable random access; read operations follow strict serial protocol timing defined in AC Characteristics tables for industrial temperature range.
Does the AT17LV128-10JI support both 3.3 V and 5.0 V operation?
Yes, the AT17LV128-10JI supports dual-voltage operation: 3.3 V ±10% and 5.0 V ±5% (commercial) or ±10% (industrial). Voltage selection is automatic-no external configuration is needed. DC and AC specifications are separately guaranteed for each supply condition, as documented in Sections 12–20 of the datasheet.
What package type is used for the AT17LV128-10JI?
The AT17LV128-10JI uses a 20-lead PLCC (Plastic Leaded Chip Carrier) package, JEDEC MS-018 compliant, with body dimensions 9.78 mm × 9.78 mm × 3.56 mm and 1.27 mm lead pitch. Pin 1 identifier is a corner chamfer, and lead coplanarity is specified ≤0.102 mm.
Can the AT17LV128-10JI be used in daisy-chain configurations?
Yes, the AT17LV128-10JI supports hardware daisy-chaining via its CEO (Chip Enable Output) pin (Pin 14), which asserts low upon completion of its internal address counter to enable the CE input of the next device in the chain. This feature is confirmed for AT17LV128 and enabled in industrial temperature grade.
What is the data retention specification for the AT17LV128-10JI at industrial temperature?
The AT17LV128-10JI guarantees 90 years of data retention at 85°C (industrial maximum operating temperature), based on EEPROM process characterization and accelerated life testing. This applies to data programmed under specified VCC and temperature conditions per Section 1 of the datasheet.
AT17LV128-10JI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 20-LCC (J-Lead)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 3V ~ 3.6V, 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-PLCC (9x9)
AT17LV128-10JI FAQ
1.How can I place an order for AT17LV128-10JI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17LV128-10JI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17LV128-10JI reliable?
The price and inventory of AT17LV128-10JI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17LV128-10JI is usually 5 days.
3.What payment methods are accepted for AT17LV128-10JI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17LV128-10JI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17LV128-10JI?
AT17LV128-10JI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17LV128-10JI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17LV128-10JI?
For technical support, including AT17LV128-10JI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17LV128-10JI requirements.
6.How does Aetrix verify that AT17LV128-10JI is sourced from the original manufacturer or authorized distributors?
All AT17LV128-10JI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17LV128-10JI meets industry standards.
7.What is the process for return or replacement of AT17LV128-10JI?
All AT17LV128-10JI units undergo pre-shipment inspection (PSI). If there is an issue with AT17LV128-10JI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17LV128-10JI part is unused and in its original packaging.
Return procedure for AT17LV128-10JI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17LV128-10JI Tags
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AT17LV512A-10PU
Microchip Technology
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EPCQ4ASI8N
Intel
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AT17LV256-10PU
Microchip Technology
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AT17LV256-10NU
Microchip Technology
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EPCQ16ASI8N
Intel
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AT17LV010-10PU
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EPCQ32ASI8N
Intel
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EPCQ64ASI16N
Intel
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EPCQ128ASI16N
Intel
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AT17LV512A-10JU
Microchip Technology
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AT17LV512-10JU
Microchip Technology
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AT17LV010-10JU
Microchip Technology
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