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Home > Products > Integrated Circuits (ICs) > Memory > Configuration PROMs for FPGAs

Microchip Technology AT17LV128-10NC

Name: AT17LV128-10NC
Brand: Microchip Technology
SKU: AT17LV128-10NC
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: AT17LV128-10NC

Manufacturer:: Microchip Technology

Category:: Configuration PROMs for FPGAs

Package:: 8-SOIC (0.154", 3.90mm Width)

Datasheet:: AT17LV128-10NC.pdf

Description:: IC EEPROM FPGA 128KB 8-SOIC

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Product details

Overview

AT17LV128-10NC from Atmel is a 128-Kbit serial FPGA configuration EEPROM designed to store and load bitstream programs for SRAM-based FPGAs in master serial mode. It supports dual-voltage operation (3.3V ±10% or 5.0V ±5%/±10%), features programmable reset polarity, offers cascading capability via CEO output, and delivers 100,000 write cycles with 90-year data retention at 85°C (industrial grade).

For engineers reviewing the AT17LV128-10NC datasheet, AT17LV128-10NC pinout, AT17LV128-10NC application, or AT17LV128-10NC equivalent, key selection criteria include its 8-lead SOIC package compatibility, 10 MHz max clock frequency at 3.3V, low-power standby current (<100 µA industrial), support for Xilinx XC4000/XC5200/Spartan and Altera FLEX/APEX devices, and in-system programmability via two-wire bus.

Technical Context

The AT17LV128-10NC operates as a dedicated serial configuration memory that interfaces directly with FPGA CCLK and DIN pins using a simple synchronous read protocol. Its internal address counter auto-resets on power-up and is controlled by CE and RESET/OE signals - the latter configurable as active-low RESET or active-high OE.

It implements cascading through the CEO output, which asserts low upon completion of data output to enable the next device in daisy-chain configurations. The SER_EN pin selects between FPGA loading mode (high) and two-wire ISP programming mode (low), with internal charge pumps eliminating need for external programming voltages.

Key Specifications

Parameter	Value and Actual Design Meaning
Memory size	128 Kbit (131,072 × 1-bit) - sufficient for mid-complexity FPGA configuration bitstreams such as Xilinx Spartan-XL or Altera FLEX 10K.
Supply voltage	3.3V ±10% or 5.0V ±5% (commercial) / ±10% (industrial) - enables drop-in use across legacy 5V and modern 3.3V FPGA systems.
Max clock frequency	10 MHz at 3.3V (industrial) - sets upper bound on configuration speed; compatible with Xilinx XC4000 master serial timing requirements.
Standby current	<100 µA at 3.3V, industrial temp - ensures minimal power draw during FPGA idle or reconfiguration hold states.
Data retention	90 years at 85°C (industrial grade) - guarantees long-term reliability in embedded control and telecom infrastructure applications.
Endurance	100,000 write cycles - supports repeated field updates and design iterations without memory wear-out concerns.
Operating temperature	–40°C to +85°C - qualified for industrial environments including motor drives, PLCs, and base station equipment.

Pinout & Package

AT17LV128-10NC is packaged in an 8-lead SOIC (JEDEC MS-012, Variation AA), pin-compatible with 8-lead LAP and PDIP footprints. This surface-mount package measures 4.9 mm × 3.9 mm × 1.75 mm and supports standard reflow profiles.

Pin	Circuit Role	Design Meaning
1 DATA	I/O (open-collector, tri-state)	Bi-directional serial data line: outputs configuration bits to FPGA DIN during read; accepts programming data during ISP.
2 CLK	Input	Drives internal address/bit counter; synchronized to FPGA CCLK - no external clock source required.
3 RESET/OE	Input	Programmable polarity pin: resets address counter when active (Low for RESET, High for OE); controls DATA driver enable.
4 CE	Input (active Low)	Enables read operation and counter increment when low; forces device into low-power standby when high.
5 GND	Power	Ground reference; requires 0.2 µF decoupling capacitor near VCC pin per datasheet recommendation.
6 CEO	Output (active Low)	Signals end-of-data to next cascaded EEPROM; essential for multi-device configuration chains (not available on AT17LV65).
7 SER_EN	Input	Selects operational mode: high = FPGA loading; low = two-wire ISP programming; tied to VCC for non-ISP use.
8 VCC	Power	Single-supply input supporting both 3.3V and 5V systems; internal regulation enables consistent EEPROM operation across voltages.

Key Features

Feature	Design Value
In-system programmability	Two-wire serial interface (SER_EN low) enables field firmware updates without socket removal or UV erasure.
Cascadable architecture	CEO output allows daisy-chaining multiple AT17LV devices to support larger FPGA bitstreams beyond 128 Kbit capacity.
Dual-voltage compatibility	Native 3.3V/5V operation eliminates level-shifting requirements when interfacing with mixed-voltage FPGA platforms.
Programmable reset polarity	User-configurable RESET/OE logic polarity accommodates both Xilinx (RESET active low) and Altera (OE active high) FPGA timing conventions.
Industrial-grade reliability	100,000 write cycles and 90-year data retention at 85°C ensure suitability for unattended, long-lifecycle industrial deployments.

Applications

Industrial PLC Configuration	Xilinx Spartan FPGA Boot
Use Scenario: Configuring SRAM-based FPGAs in programmable logic controllers deployed in factory automation systems requiring long-term field reliability. IC Role / Device Role / Timing Role: Stores and serially loads FPGA bitstream at power-up; synchronizes to FPGA CCLK with precise TOE/TCE timing margins. Use Value: Eliminates external microcontroller dependency for configuration, reduces BOM count, and ensures deterministic boot within 10 ms at 10 MHz clock.	Use Scenario: Booting Xilinx Spartan-XL FPGAs in cost-sensitive communications edge devices where space and power are constrained. IC Role / Device Role / Timing Role: Acts as master serial configuration memory; interfaces directly with Spartan DIN/CCLK/INIT pins using standard timing waveforms. Use Value: Enables single-chip FPGA boot solution with <100 µA standby current, supporting battery-backed or energy-harvesting designs.
Altera FLEX 10K System Boot	Cascaded Multi-FPGA Systems
Use Scenario: Loading configuration data for Altera FLEX 10K series FPGAs in legacy industrial instrumentation with 5V system rails. IC Role / Device Role / Timing Role: Provides OE-active-high interface matching FLEX device requirements; supports 5V ±10% operation without voltage translation. Use Value: Ensures full compatibility with Altera's master serial protocol while maintaining pinout and timing compliance per datasheet AC specs.	Use Scenario: Supporting large-scale FPGA arrays in radar signal processing modules requiring >128 Kbit total configuration storage. IC Role / Device Role / Timing Role: First-stage configurator in daisy chain; uses CEO output to trigger CE of subsequent AT17LV device upon data exhaustion. Use Value: Enables scalable configuration memory expansion up to 4 Mbit (AT17LV040) using identical control logic and timing behavior across all stages.

Industrial PLC Configuration

Xilinx Spartan FPGA Boot

Use Scenario: Configuring SRAM-based FPGAs in programmable logic controllers deployed in factory automation systems requiring long-term field reliability.

IC Role / Device Role / Timing Role: Stores and serially loads FPGA bitstream at power-up; synchronizes to FPGA CCLK with precise TOE/TCE timing margins.

Use Value: Eliminates external microcontroller dependency for configuration, reduces BOM count, and ensures deterministic boot within 10 ms at 10 MHz clock.

Use Scenario: Booting Xilinx Spartan-XL FPGAs in cost-sensitive communications edge devices where space and power are constrained.

IC Role / Device Role / Timing Role: Acts as master serial configuration memory; interfaces directly with Spartan DIN/CCLK/INIT pins using standard timing waveforms.

Use Value: Enables single-chip FPGA boot solution with <100 µA standby current, supporting battery-backed or energy-harvesting designs.

Altera FLEX 10K System Boot

Cascaded Multi-FPGA Systems

Use Scenario: Loading configuration data for Altera FLEX 10K series FPGAs in legacy industrial instrumentation with 5V system rails.

IC Role / Device Role / Timing Role: Provides OE-active-high interface matching FLEX device requirements; supports 5V ±10% operation without voltage translation.

Use Value: Ensures full compatibility with Altera's master serial protocol while maintaining pinout and timing compliance per datasheet AC specs.

Use Scenario: Supporting large-scale FPGA arrays in radar signal processing modules requiring >128 Kbit total configuration storage.

IC Role / Device Role / Timing Role: First-stage configurator in daisy chain; uses CEO output to trigger CE of subsequent AT17LV device upon data exhaustion.

Use Value: Enables scalable configuration memory expansion up to 4 Mbit (AT17LV040) using identical control logic and timing behavior across all stages.

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Xilinx XC18V02	2-Mbit serial PROM; 3.3V only; no 5V support; different pinout (20-pin PLCC/SOIC); lacks CEO cascading output.	Targeted exclusively at Xilinx FPGA ecosystems; not interoperable with Altera or Atmel FPGA families.	Choose when upgrading from AT17LV128-10NC to higher-density Xilinx-only systems and 5V compatibility is unnecessary.
Microchip 25LC1024	1-Mbit SPI EEPROM; 2.5–5.5V supply; no built-in FPGA timing control logic; requires external controller for configuration sequencing.	General-purpose SPI memory - lacks native master serial mode support, CEO signaling, or programmable reset polarity.	Choose only if adding MCU-level control is acceptable and FPGA vendor-agnostic configuration flexibility is prioritized over simplicity.

Compared with AT17LV128-10NC, XC18V02 offers higher density but sacrifices 5V operation and cross-vendor compatibility, while 25LC1024 provides SPI universality at the cost of added firmware complexity and loss of autonomous FPGA boot capability.

Availability

AT17LV128-10NC is available at Aetrix Electronics and suitable for industrial automation, FPGA-based communications equipment, and embedded control systems requiring stable component supply, long-life qualification, and RoHS-compliant packaging.

Supply support for AT17LV128-10NC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions for industrial, automotive, and communications markets.

The AT17LV series was designed specifically to simplify and harden FPGA configuration in resource-constrained embedded systems - delivering plug-and-play bitstream loading without external logic or software intervention.

FAQ

What is the primary function of the AT17LV128-10NC in an FPGA system?

The AT17LV128-10NC serves as a dedicated serial configuration memory that stores and automatically loads the bitstream into SRAM-based FPGAs during power-up or reset. It interfaces directly with FPGA control signals (CCLK, DIN, INIT) in master serial mode, eliminating the need for an external controller. The AT17LV128-10NC handles address counting, data output timing, and cascading coordination - making it a self-contained, hardware-driven boot solution for Xilinx, Altera, and Atmel FPGAs.

Does the AT17LV128-10NC support both 3.3V and 5V FPGA systems?

Yes, the AT17LV128-10NC supports dual-voltage operation: 3.3V ±10% and 5.0V ±5% (commercial) or ±10% (industrial). Its I/O thresholds and internal regulation allow direct connection to either voltage domain without level shifters. This makes the AT17LV128-10NC suitable for legacy 5V designs and modern 3.3V FPGA platforms - including Xilinx XC4000, Spartan, and Altera FLEX 10K families - while maintaining full AC timing compliance in both modes.

Can the AT17LV128-10NC be programmed in-circuit after soldering?

Yes, the AT17LV128-10NC supports in-system programming (ISP) via its two-wire serial interface when SER_EN is pulled low. This allows field updates of FPGA configuration data without removing the device from the PCB. Programming occurs at the same VCC supply voltage (no external VPP required), using standard industry programmers or Atmel's ATDH2225 ISP Cable. The AT17LV128-10NC retains full functionality during ISP, with dedicated WP and SER_EN pins ensuring safe, controlled memory writes.

How does cascading work with multiple AT17LV128-10NC devices?

Cascading uses the CEO (Chip Enable Output) pin of one AT17LV128-10NC to drive the CE (Chip Enable) input of the next device in the chain. When the first device outputs its final bit, CEO goes low, enabling the second device's DATA output. This daisy-chain mechanism allows seamless expansion beyond 128 Kbit - for example, two AT17LV128-10NC units provide 256 Kbit total. The AT17LV128-10NC's CEO feature is fully compatible with the timing requirements of Xilinx and Altera master serial protocols.

What is the significance of programmable reset polarity in the AT17LV128-10NC?

The AT17LV128-10NC allows users to configure the RESET/OE pin as either active-low RESET (for Xilinx FPGAs) or active-high OE (for Altera FLEX/APEX devices) via EEPROM programming. This eliminates board-level redesign when switching FPGA vendors or families. The setting persists across power cycles and is verified during initialization. Because the AT17LV128-10NC handles this logic internally, designers retain full timing compliance without external glue logic - a key advantage over generic SPI EEPROMs.

AT17LV128-10NC Specifications

Product attributes: Attribute value

Manufacturer:: Microchip Technology

Series:: -

Package/Case:: 8-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Programmable:: Not Verified

Programmable Type:: Serial EEPROM

Memory Size:: 128kb

Voltage - Supply:: 3V ~ 3.6V, 4.75V ~ 5.25V

Operating Temperature:: 0°C ~ 70°C

Mounting Type:: Surface Mount

Supplier Device Package:: 8-SOIC

AT17LV128-10NC FAQ

1.How can I place an order for AT17LV128-10NC through Aetrix?

Please submit a Request for Quotation (RFQ) for AT17LV128-10NC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for AT17LV128-10NC reliable?

The price and inventory of AT17LV128-10NC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17LV128-10NC is usually 5 days.

3.What payment methods are accepted for AT17LV128-10NC?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17LV128-10NC transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for AT17LV128-10NC?

AT17LV128-10NC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your AT17LV128-10NC order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for AT17LV128-10NC?

For technical support, including AT17LV128-10NC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17LV128-10NC requirements.

6.How does Aetrix verify that AT17LV128-10NC is sourced from the original manufacturer or authorized distributors?

All AT17LV128-10NC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17LV128-10NC meets industry standards.

7.What is the process for return or replacement of AT17LV128-10NC?

All AT17LV128-10NC units undergo pre-shipment inspection (PSI). If there is an issue with AT17LV128-10NC, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The AT17LV128-10NC part is unused and in its original packaging.

Return procedure for AT17LV128-10NC:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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