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Microchip Technology AT17LV128-10NI
- Part No.:
- AT17LV128-10NI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT17LV128-10NI.pdf
- Description:
- IC EEPROM FPGA 128KB 8-SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:3,804
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Product details
Overview
AT17LV128-10NI from Atmel is a 128-Kbit (131,072 × 1-bit) serial FPGA configuration EEPROM designed for reliable, in-system programmable storage of SRAM-based FPGA bitstreams. It operates at both 3.3V and 5.0V, supports cascaded daisy-chain configurations via CEO output, and features programmable reset polarity for compatibility with Xilinx XC3000/XC4000, Altera FLEX/APEX, and Atmel AT40K/AT94K FPGAs.
For engineers reviewing the AT17LV128-10NI datasheet, AT17LV128-10NI pinout, AT17LV128-10NI application, or AT17LV128-10NI equivalent, key selection criteria include industrial temperature range (–40°C to +85°C), 8-lead SOIC package compatibility, low-power standby current (≤100 µA at 3.3V), cascading capability via CEO, and dual-voltage support for legacy and modern FPGA systems.
Technical Context
The AT17LV128-10NI implements a serial master-mode configuration interface synchronized to an external FPGA CCLK signal, with CE, RESET/OE, and SER_EN controlling address counter enablement, reset behavior, and ISP mode entry. Its internal EEPROM array is accessed via a simple three-wire protocol (CLK, DATA, CE) during FPGA boot, eliminating need for external controllers.
It supports two distinct operational modes: FPGA loading (SER_EN = High) and Two-Wire ISP programming (SER_EN = Low). In loading mode, it delivers configuration data on DATA with timing governed by TCAC (CLK-to-data delay ≤80 ns at 3.3V), while CEO asserts low upon completion to enable chaining to subsequent configurators.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (131,072 × 1-bit) - sufficient for mid-complexity Xilinx XC4000 or Altera FLEX 10K FPGA configurations |
| Supply voltage | 3.3V ±10% or 5.0V ±5% (Commercial) / ±10% (Industrial) - enables drop-in replacement in mixed-voltage legacy and new designs |
| Operating temperature | –40°C to +85°C - qualified for industrial embedded control, motor drives, and telecom infrastructure |
| Standby current | ≤100 µA at 3.3V (Industrial) - minimizes system power draw when FPGA is not configuring |
| Endurance & retention | 100,000 write cycles; 90-year data retention at 85°C - ensures long-term field reliability without refresh |
| Max clock frequency | 10 MHz (3.3V, Industrial); 12.5 MHz (5V, Commercial) - matches standard FPGA CCLK timing budgets |
| Cascading support | CEO output (active-low) - enables automatic handoff to next EEPROM in daisy chain without external logic |
Pinout & Package
AT17LV128-10NI is supplied in an 8-lead SOIC (8S1) package, pin-compatible with industry-standard 8-lead SOIC footprints and functionally identical to the 8-lead LAP variant for layout interchangeability.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 (DATA) | Bi-directional I/O | Three-state open-collector output during FPGA load; bidirectional for ISP programming |
| 2 (CLK) | Input | Edge-triggered clock input driving internal address/bit counter; synchronous with FPGA CCLK |
| 3 (RESET/OE) | Input | Programmable polarity pin: active-Low reset + active-High output enable; controls DATA driver and counter reset |
| 4 (CE) | Input | Chip Enable (active-Low); enables CLK-driven counting and DATA output; forces standby when high |
| 5 (GND) | Power | Ground reference; requires 0.2 µF decoupling capacitor per datasheet recommendation |
| 6 (CEO) | Output | Chip Enable Output (active-Low); signals end-of-data to next device in cascade chain |
| 7 (SER_EN) | Input | Serial Enable (High = FPGA load mode; Low = Two-Wire ISP mode); tied to VCC in non-programming use |
| 8 (VCC) | Power | 3.3V or 5.0V supply input; supports dual-voltage system integration without level shifters |
Key Features
| Feature | Design Value |
|---|---|
| In-System Programmability (ISP) | Two-wire serial programming via SER_EN-controlled mode eliminates need for dedicated programmers in field updates |
| Dual-voltage operation | Single device supports both 3.3V and 5.0V FPGA platforms, reducing BOM count and simplifying design reuse |
| Cascadable CEO output | Enables seamless expansion beyond 128 Kbit using multiple AT17LV devices without external glue logic or timing compensation |
| Programmable reset polarity | User-configurable RESET/OE logic allows alignment with FPGA-specific reset timing requirements (e.g., Xilinx vs. Altera conventions) |
| Low-power standby | ≤100 µA ICCS at 3.3V/85°C enables energy-sensitive applications like remote sensors and battery-backed systems |
| Industrial-grade reliability | 90-year data retention at 85°C and 100,000 write cycles ensure long service life in unattended equipment |
Applications
| Industrial PLC Configuration | Xilinx XC4000-Based Prototyping |
|---|---|
Use Scenario: Reconfiguring FPGA logic in programmable logic controllers deployed in factory automation environments with wide ambient temperature swings. IC Role / Device Role / Timing Role: Stores and serially delivers bitstream to Xilinx XC4000 FPGA upon power-up or command; CEO synchronizes multi-FPGA reload sequences. Use Value: Eliminates external microcontroller dependency for configuration management and ensures deterministic boot within industrial thermal limits (–40°C to +85°C). |
Use Scenario: Rapid iteration of FPGA-based digital signal processing cores on lab evaluation boards using Xilinx XC4000-series devices. IC Role / Device Role / Timing Role: Provides nonvolatile, reprogrammable configuration memory compatible with Xilinx Master Serial mode; supports in-circuit updates via ISP. Use Value: Enables fast design verification cycles without socketing or external programming hardware-reducing development time and board complexity. |
| Altera FLEX 10K Motor Control | Legacy 5V System Migration |
Use Scenario: Configuring Altera FLEX 10K FPGAs in servo drive controllers where real-time responsiveness and field firmware updates are critical. IC Role / Device Role / Timing Role: Acts as primary configuration source in Master Serial mode; CEO output chains to auxiliary memory for extended gate count support. Use Value: Guarantees sub-100 ns timing margins (TCAC ≤80 ns at 3.3V) required for deterministic motor commutation timing across temperature. |
Use Scenario: Upgrading aging 5V-only industrial systems to support newer 3.3V FPGAs while retaining existing PCB layouts and power architecture. IC Role / Device Role / Timing Role: Dual-voltage operation allows direct substitution into legacy 5V sockets while enabling future 3.3V FPGA integration. Use Value: Avoids costly PCB redesign; maintains full functionality across voltage transitions without performance or timing degradation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT17LV128-10PI | Same 128-Kbit capacity and pinout, but packaged in 8-lead PDIP (8P3) instead of SOIC; higher θJA (107°C/W vs. 150°C/W) | Better suited for through-hole prototyping or legacy repair; less suitable for high-density SMT production | Select for hand-soldered development or field replacement where SOIC footprint is unavailable |
| XCR3256XL-10TQ144I | Not a configuration EEPROM - is a CPLD with integrated configuration logic; requires different FPGA interface and lacks CEO cascading | Used for small-scale logic replacement, not bitstream storage; no native support for Xilinx Master Serial mode | Only consider if replacing both configuration memory and glue logic - not a functional substitute for AT17LV128-10NI |
Compared with AT17LV128-10PI, the AT17LV128-10NI offers superior thermal performance in SMT assemblies and smaller board footprint; compared with XCR3256XL-10TQ144I, it provides dedicated, standards-compliant FPGA configuration with proven timing compliance and zero FPGA-side logic overhead.
Availability
AT17LV128-10NI is available at Aetrix Electronics and suitable for industrial automation, FPGA-based prototyping, motor control systems, and legacy 5V-to-3.3V migration projects requiring stable component supply across extended product lifecycles.
Supply support for AT17LV128-10NI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions for industrial, automotive, and communications markets.
The AT17LV series was designed specifically to provide robust, pin-compatible configuration memory for SRAM-based FPGAs-including Xilinx, Altera, and Atmel's own families-with emphasis on industrial temperature operation, low-power standby, and seamless daisy-chaining.
FAQ
What is the maximum clock frequency supported by the AT17LV128-10NI during FPGA configuration?
The AT17LV128-10NI supports up to 10 MHz at 3.3V under industrial conditions (–40°C to +85°C) and up to 12.5 MHz at 5.0V under commercial conditions (0°C to +70°C), as specified in AC Characteristics Tables 17 and 19. These values ensure reliable timing margin compliance with Xilinx XC4000 and Altera FLEX 10K FPGA CCLK requirements. The AT17LV128-10NI must be operated within these limits to guarantee correct bitstream delivery without read errors.
Does the AT17LV128-10NI support cascading with other AT17LV devices?
Yes, the AT17LV128-10NI supports hardware cascading via its CEO (Chip Enable Output) pin, which goes active-Low when the internal address counter reaches its final location. This signal directly drives the CE input of the next AT17LV device in a daisy chain, enabling automatic handoff without external logic. Cascading is fully documented in Section 7 of the datasheet and verified for AT17LV128-10NI in 8-lead SOIC and LAP packages.
Can the AT17LV128-10NI be programmed in-circuit after soldering to the PCB?
Yes, the AT17LV128-10NI supports In-System Programming (ISP) via its Two-Wire Serial interface when SER_EN is pulled Low. This allows field firmware updates without removing the device from the board. Programming uses standard VCC supply voltage only-no external high-voltage programming signals are required-and is compatible with Atmel's ATDH2225 ISP Cable or third-party programmers supporting the AT17LV command set.
What is the operating temperature range for the AT17LV128-10NI?
The AT17LV128-10NI is rated for industrial operation from –40°C to +85°C, as indicated by the "I" suffix in its ordering code. This range is validated per Absolute Maximum Ratings and Operating Conditions (Section 11 and 12), and all DC and AC specifications-including standby current (≤100 µA), timing parameters, and data retention (90 years at 85°C)-are guaranteed across this full span. The AT17LV128-10NI is not rated for automotive or extended temperature use.
Is the AT17LV128-10NI pin-compatible with other members of the AT17LV family?
The AT17LV128-10NI shares identical pinout and functionality with AT17LV65-10NI and AT17LV256-10NI in 8-lead SOIC (8S1) and LAP (8CN4) packages, as confirmed in Table 1-1 and Figure 2-1/2-2. However, it is not pin-compatible with AT17LV512-10NI or higher-density variants, which require 20-lead PLCC/SOIC or 44-lead TQFP packages and feature additional pins (e.g., WP1, WP2, READY) absent in the AT17LV128-10NI.
AT17LV128-10NI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 3V ~ 3.6V, 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT17LV128-10NI FAQ
1.How can I place an order for AT17LV128-10NI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17LV128-10NI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17LV128-10NI reliable?
The price and inventory of AT17LV128-10NI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17LV128-10NI is usually 5 days.
3.What payment methods are accepted for AT17LV128-10NI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17LV128-10NI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17LV128-10NI?
AT17LV128-10NI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17LV128-10NI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17LV128-10NI?
For technical support, including AT17LV128-10NI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17LV128-10NI requirements.
6.How does Aetrix verify that AT17LV128-10NI is sourced from the original manufacturer or authorized distributors?
All AT17LV128-10NI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17LV128-10NI meets industry standards.
7.What is the process for return or replacement of AT17LV128-10NI?
All AT17LV128-10NI units undergo pre-shipment inspection (PSI). If there is an issue with AT17LV128-10NI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17LV128-10NI part is unused and in its original packaging.
Return procedure for AT17LV128-10NI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17LV128-10NI Tags
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AT17LV512A-10PU
Microchip Technology
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EPCQ4ASI8N
Intel
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AT17LV256-10PU
Microchip Technology
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AT17LV256-10NU
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EPCQ16ASI8N
Intel
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AT17LV010-10PU
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EPCQ32ASI8N
Intel
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EPCQ64ASI16N
Intel
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EPCQ128ASI16N
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AT17LV512A-10JU
Microchip Technology
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AT17LV512-10JU
Microchip Technology
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AT17LV010-10JU
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