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Microchip Technology AT17LV128-10PC
- Part No.:
- AT17LV128-10PC
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
AT17LV128-10PC.pdf
- Description:
- IC SER CNFIG PROM 128K 3.3V 8DIP
- Quantity:
- Payment:
- Shipping:
Inventory:2,608
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Product details
Overview
AT17LV128-10PC from Atmel is a 128-Kbit serial FPGA configuration EEPROM designed for master-serial mode loading of SRAM-based FPGAs. It supports dual-voltage operation (3.3V ±10% or 5.0V ±5%/±10%), offers in-system programmability via two-wire bus, and features programmable reset polarity and cascading CEO output for multi-device chains. Used in industrial control logic and reconfigurable computing systems requiring reliable, low-power nonvolatile configuration storage.
For engineers reviewing the AT17LV128-10PC datasheet, AT17LV128-10PC pinout, AT17LV128-10PC application, or AT17LV128-10PC equivalent, key selection criteria include its 128-Kbit density, 8-lead PDIP package compatibility, support for Xilinx XC4000/Virtex and Altera FLEX/APEX FPGAs, and verified 100,000 write-cycle endurance with 90-year data retention at 85°C.
Technical Context
The AT17LV128-10PC implements a serial address counter architecture synchronized to an external FPGA CCLK signal, enabling direct master-serial configuration without host controller intervention. Its RESET/OE pin serves dual function-active-low reset and active-high output enable-with polarity programmable via EEPROM bytes.
It supports cascading via CEO (Chip Enable Output), which asserts low upon completion of readout to enable the next device in daisy-chain topology. Standby current is <50 µA at 3.3V (commercial) and <100 µA (industrial), achieved by CE-driven power-down mode independent of SER_EN state.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (131,072 × 1-bit) - matches AT17LV128 family designation and enables full configuration of mid-density FPGAs like Xilinx XC4010 or Altera EPF10K10. |
| Supply voltage | 3.3V ±10% or 5.0V ±5% (commercial), ±10% (industrial) - dual-rail support simplifies integration into mixed-voltage FPGA systems without level-shifting. |
| Max clock frequency | 12.5 MHz at 5V (commercial) - ensures fast configuration load times compatible with FPGA CCLK requirements up to 12.5 MHz. |
| Write endurance | 100,000 cycles - sufficient for repeated firmware updates and field reprogramming during development and maintenance cycles. |
| Data retention | 90 years at 85°C (industrial grade) - guarantees long-term reliability in embedded industrial environments without refresh. |
| Standby current | <50 µA at 3.3V (commercial), <100 µA (industrial) - enables ultra-low-power system sleep states while preserving configuration readiness. |
| Operating temperature | –40°C to +85°C (industrial) - validated for deployment in harsh environments including factory automation and outdoor telecom equipment. |
Pinout & Package
AT17LV128-10PC is packaged in an 8-lead plastic dual inline package (PDIP), 0.300" wide, with JEDEC-standard footprint and pinout identical to industry-standard 8-pin SOIC/LAP devices. Pin 1 is marked with notch or dot; body dimensions are 0.355" × 0.300" × 0.130".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 DATA | I/O (open-collector) | Bi-directional serial data line: outputs configuration bits to FPGA DIN during load; accepts programming data during ISP mode. |
| 2 CLK | Input | Master clock input driven by FPGA CCLK; increments internal address/bit counter on rising edge for synchronous readout. |
| 3 RESET/OE | Input | Programmable dual-function pin: active-low reset (resets address counter) and active-high output enable (controls DATA driver). |
| 4 CE | Input (active low) | Chip enable: disables address counter and forces DATA into high-impedance when high; enters low-power standby mode. |
| 5 GND | Power | Ground reference; requires 0.2 µF decoupling capacitor near VCC pin per design guidelines. |
| 6 CEO | Output (active low) | Cascading output: goes low when last bit is read, enabling CE of next EEPROM in daisy chain; not present on AT17LV65. |
| 7 SER_EN | Input | Serial enable: must be tied high for FPGA configuration; pulled low to enter two-wire ISP programming mode. |
| 8 VCC | Power | 3.3V or 5.0V supply input; tolerates ±10% variation at 3.3V, ±5%/±10% at 5V depending on grade. |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Two-wire serial interface (SER_EN + DATA/CLK) enables field firmware updates without removing device from PCB. |
| Cascadable CEO output | Enables daisy-chained configuration of multiple FPGAs or higher-density memory expansion using single CCLK source. |
| Programmable reset polarity | User-configurable RESET/OE logic polarity via EEPROM byte programming, matching diverse FPGA reset architectures. |
| Low-power standby mode | CE-driven standby draws <50 µA at 3.3V, reducing system power budget during idle or sleep states. |
| Emulation of AT24CXXX EEPROMs | Compatible with standard I²C-like programmers and software tools, lowering development tooling cost and integration effort. |
Applications
| Industrial PLC Configuration Storage | Xilinx Virtex FPGA Boot Loader |
|---|---|
Use Scenario: Storing bitstream for reconfigurable logic in programmable logic controllers deployed in factory-floor automation cabinets. IC Role / Device Role / Timing Role: Master-serial configuration EEPROM providing deterministic, power-on self-load of FPGA gate array without external microcontroller. Use Value: Eliminates need for external boot processor; supports hot-swap reconfiguration via ISP; retains configuration across 100,000+ power cycles. | Use Scenario: Loading initial configuration for Xilinx Virtex-4 FPGA in high-speed test equipment requiring rapid reconfiguration between test vectors. IC Role / Device Role / Timing Role: Serial configuration memory synchronized to FPGA CCLK, delivering 128-Kbit bitstream at up to 12.5 MHz. Use Value: Meets Virtex-4 master-serial timing requirements; CEO output enables seamless chaining with auxiliary memory for larger designs. |
| Altera FLEX10K System Initialization | Multi-FPGA Telecommunications Baseband |
Use Scenario: Power-up initialization of Altera FLEX10K10 FPGA used in legacy telecom line cards operating in extended temperature range. IC Role / Device Role / Timing Role: Industrial-grade (–40°C to +85°C) configuration memory with 90-year data retention, directly interfacing with FLEX10K CCLK and DATA_IN pins. Use Value: Guarantees reliable startup after decades of field deployment; supports in-circuit programming via Atmel ATDH2225 ISP cable. | Use Scenario: Cascaded configuration of three Xilinx Spartan-II FPGAs in a wireless baseband processing module requiring synchronized bitstream load. IC Role / Device Role / Timing Role: First-stage EEPROM in daisy chain; CEO output triggers CE of second device, enabling sequential load without additional control logic. Use Value: Reduces PCB routing complexity vs. parallel configuration; maintains timing integrity across all devices using single CCLK source. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Xilinx XC18V02 | 2-Mbit density, 3.3V-only supply, no CEO output, different pinout (20-pin PLCC only) | Supports larger FPGAs (e.g., XC2VP7); lacks cascading capability and dual-voltage operation | Select when higher density is required and cascading is unnecessary; verify PCB layout compatibility due to 20-pin PLCC footprint. |
| Microchip 25LC1024 | 1-Mbit SPI EEPROM, 2.5–5.5V supply, no built-in FPGA interface logic or CEO output | Requires external FPGA logic to implement serial configuration protocol; no native master-serial mode support | Choose only if custom configuration controller is already implemented; adds design complexity versus plug-and-play AT17LV128-10PC. |
Compared with XC18V02 and 25LC1024, the AT17LV128-10PC delivers purpose-built FPGA configuration functionality-including CEO cascading, programmable reset polarity, and guaranteed master-serial timing-within a compact 8-pin PDIP package supporting both 3.3V and 5V systems.
Availability
AT17LV128-10PC is available at Aetrix Electronics and suitable for industrial automation, telecommunications infrastructure, and reconfigurable computing applications requiring stable component supply, long-life product support, and RoHS-compliant sourcing.
Supply support for AT17LV128-10PC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions.
The AT17LV series was designed specifically for reliable, low-power, serial configuration of SRAM-based FPGAs in industrial and commercial systems, emphasizing ease of integration, in-system programmability, and long-term data retention.
FAQ
What is the memory capacity of the AT17LV128-10PC?
The AT17LV128-10PC provides 128 Kbit (131,072 × 1-bit) of EEPROM storage, optimized to hold the complete configuration bitstream for mid-density SRAM-based FPGAs such as Xilinx XC4010 or Altera EPF10K10. This capacity is fixed and cannot be expanded or reduced via configuration.
Does the AT17LV128-10PC support both 3.3V and 5.0V operation?
Yes, the AT17LV128-10PC supports dual-voltage operation: 3.3V ±10% or 5.0V ±5% (commercial grade) and ±10% (industrial grade). Voltage selection is determined by the applied VCC; no external configuration or mode pin is required, enabling flexible use across mixed-voltage FPGA platforms.
Can the AT17LV128-10PC be programmed in-circuit?
Yes, the AT17LV128-10PC supports in-system programming (ISP) via its two-wire serial interface when SER_EN is pulled low. Programming can be performed using industry-standard programmers or Atmel's ATDH2225 ISP Cable, allowing field updates without device removal.
What is the role of the CEO pin on the AT17LV128-10PC?
The CEO (Chip Enable Output) pin on the AT17LV128-10PC is an active-low signal that asserts after the final bit is read, enabling the CE input of the next AT17LV-series device in a daisy chain. This allows automatic cascading of configuration memory for multi-FPGA systems or higher-density bitstreams without external logic.
Is the AT17LV128-10PC pin-compatible with other AT17LV family members?
No, the AT17LV128-10PC shares pinout compatibility only with AT17LV65 and AT17LV256 (all 8-lead variants), but is not pin-compatible with AT17LV512/010/002/040 devices, which use different pin assignments and feature sets (e.g., WP1/WP2, READY). Always consult Table 1-1 and Figures 2-1 through 2-3 for exact package mapping.
AT17LV128-10PC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 3V ~ 3.6V, 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
AT17LV128-10PC FAQ
1.How can I place an order for AT17LV128-10PC through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17LV128-10PC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17LV128-10PC reliable?
The price and inventory of AT17LV128-10PC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17LV128-10PC is usually 5 days.
3.What payment methods are accepted for AT17LV128-10PC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17LV128-10PC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17LV128-10PC?
AT17LV128-10PC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17LV128-10PC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17LV128-10PC?
For technical support, including AT17LV128-10PC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17LV128-10PC requirements.
6.How does Aetrix verify that AT17LV128-10PC is sourced from the original manufacturer or authorized distributors?
All AT17LV128-10PC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17LV128-10PC meets industry standards.
7.What is the process for return or replacement of AT17LV128-10PC?
All AT17LV128-10PC units undergo pre-shipment inspection (PSI). If there is an issue with AT17LV128-10PC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17LV128-10PC part is unused and in its original packaging.
Return procedure for AT17LV128-10PC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17LV128-10PC Tags
-
AT17LV512A-10PU
Microchip Technology
-
EPCQ4ASI8N
Intel
-
AT17LV256-10PU
Microchip Technology
-
AT17LV256-10NU
Microchip Technology
-
EPCQ16ASI8N
Intel
-
AT17LV010-10PU
Microchip Technology
-
EPCQ32ASI8N
Intel
-
EPCQ64ASI16N
Intel
-
EPCQ128ASI16N
Intel
-
AT17LV512A-10JU
Microchip Technology
-
AT17LV512-10JU
Microchip Technology
-
AT17LV010-10JU
Microchip Technology
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