Microchip Technology AT17LV128-10SC

Overview

AT17LV128-10SC from Atmel is a 128-Kbit serial FPGA configuration EEPROM designed to store bitstream programs for SRAM-based FPGAs in master serial mode. It supports dual-voltage operation (3.3V ±10% or 5.0V ±5%/±10%), features programmable reset polarity, offers 100,000 write cycles and 90-year data retention at 85°C (industrial), and is packaged in a 20-lead SOIC. It interfaces directly with Xilinx XC3000/XC4000/Spartan, Altera FLEX/APEX, and Atmel AT40K/AT94K FPGAs.

For engineers reviewing the AT17LV128-10SC datasheet, AT17LV128-10SC pinout, AT17LV128-10SC application, or AT17LV128-10SC equivalent, key selection criteria include cascading support via CEO output, in-system programmability via two-wire bus, low-power standby current (≤100 µA at 3.3V industrial), compatibility with industry-standard FPGA master serial protocols, and RoHS-compliant green packaging options.

Technical Context

The AT17LV128-10SC operates as a dedicated serial configuration memory that loads bitstreams into SRAM-based FPGAs upon power-up or command. Its control logic synchronizes with FPGA CCLK, uses RESET/OE for counter reset and output enable, and employs CE to gate address counting and DATA output. The device implements a simple address counter architecture with automatic power-on reset and tri-state DATA output driven by OE/CE/CEO states.

It supports cascaded daisy-chain configurations using the CEO output to enable subsequent devices, requires SER_EN tied high during FPGA loading, and enters two-wire ISP mode only when SER_EN is pulled low. The internal EEPROM array is organized as 131,072 × 1-bit, with write protection controlled by WP input (active-high) and programmable reset polarity stored in EEPROM bytes.

Key Specifications

Pinout & Package

The AT17LV128-10SC is supplied in a 20-lead SOIC package (20S2), 0.300" wide, with JEDEC-compliant gull-wing leads and 1.27 mm pitch. Pin 1 is marked by a beveled corner; the package footprint is compatible with standard SOIC-20 PCB layouts.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with XC18V02 and MX25L12835F, the AT17LV128-10SC delivers native FPGA master serial compatibility, seamless cascading via CEO, and true dual-voltage operation-making it optimal for cost-sensitive, industrial-grade FPGA boot systems where simplicity, reliability, and pin-compatible upgrades matter most.

Availability

AT17LV128-10SC is available at Aetrix Electronics and suitable for industrial PLCs, FPGA-based test equipment, communication gateways, and embedded controllers requiring stable component supply, long-life data retention, and RoHS-compliant packaging.

Supply support for AT17LV128-10SC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Atmel Corporation (now part of Microchip Technology) is a semiconductor manufacturer specializing in microcontrollers, nonvolatile memory, and FPGA configuration solutions.

The AT17LV series was designed specifically as serial configuration EEPROMs for SRAM-based FPGAs, emphasizing plug-and-play integration, industrial reliability, and compatibility with Xilinx, Altera, and Atmel FPGA families.

FAQ

What is the memory organization of the AT17LV128-10SC?

The AT17LV128-10SC contains 131,072 bits of EEPROM memory arranged as a 131,072 × 1-bit serial array. This structure is optimized for sequential bitstream loading in FPGA master serial mode, with no internal addressing logic required beyond the linear counter. The device does not support byte-wide or random-access reads - all operations follow strict serial protocol timing defined in the datasheet.

Does the AT17LV128-10SC support cascading with other configuration EEPROMs?

Yes, the AT17LV128-10SC supports cascading via its CEO (Chip Enable Output) pin (Pin 14). When the internal address counter reaches its maximum value, CEO asserts low to enable the CE input of the next AT17LV-series device in the daisy chain. This feature is confirmed for AT17LV128-10SC in the pin description table and Figure 2-5, and enables multi-device configuration without external glue logic.

What is the function of the SER_EN pin on the AT17LV128-10SC?

The SER_EN pin (Pin 17) on the AT17LV128-10SC must be held high during normal FPGA configuration loading to enable master serial mode. Pulling SER_EN low activates the two-wire in-system programming interface, allowing reprogramming via external programmer. For fixed-function applications, SER_EN is typically tied to VCC; its state directly determines operational mode and cannot be left floating.

Can the AT17LV128-10SC operate at both 3.3V and 5.0V supply voltages?

Yes, the AT17LV128-10SC is fully specified for dual-voltage operation: 3.3V ±10% and 5.0V ±5% (commercial) or ±10% (industrial). DC and AC characteristics are separately guaranteed for each voltage, and the device automatically adapts logic thresholds and drive strength. This eliminates need for level shifters when interfacing with mixed-voltage FPGA platforms.

Is the AT17LV128-10SC pin-compatible with other AT17LV family members?

No - the AT17LV128-10SC in 20-lead SOIC (20S2) shares pinout compatibility only with AT17LV65/128/256 devices in the same package variant (per Note 1 in Figure 2-5). It is not pin-compatible with AT17LV512/010/002/040 devices, which use different pin assignments for WP1, WP2, READY, and A2 functions. Always consult Table 1-1 and Figures 2-5/2-6 for exact variant mapping.