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Microchip Technology AT17LV128-10SI
- Part No.:
- AT17LV128-10SI
- Manufacturer:
- Microchip Technology
- Category:
- Configuration PROMs for FPGAs
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
AT17LV128-10SI.pdf
- Description:
- IC SRL CONFIG EEPROM 128K 20SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,306
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Product details
Overview
AT17LV128-10SI from Microchip Technology (formerly Atmel) is a 128-Kbit serial FPGA configuration EEPROM designed for master-serial mode loading of SRAM-based FPGAs. It supports dual-voltage operation (3.3V ±10% or 5.0V ±5%/±10%), offers in-system programmability via two-wire bus, and provides cascading capability through CEO output. It is used in industrial embedded systems requiring reliable, low-power nonvolatile configuration storage.
For engineers reviewing the AT17LV128-10SI datasheet, AT17LV128-10SI pinout, AT17LV128-10SI application, or AT17LV128-10SI equivalent, key selection criteria include industrial temperature range (–40°C to +85°C), 20-lead SOIC package compatibility, programmable reset polarity, cascading support for multi-FPGA systems, and EEPROM endurance of 100,000 write cycles with 90-year data retention at 85°C.
Technical Context
The AT17LV128-10SI implements a serial address counter architecture synchronized to an external FPGA-provided CLK signal. Its RESET/OE pin serves dual functions-active-low reset and active-high output enable-with polarity programmable via internal EEPROM bytes. The device enters low-power standby (<100 µA at 3.3V industrial) when CE is high, and supports daisy-chained configurations via CEO output that asserts low upon end-of-data to enable the next device.
It operates in two distinct modes: FPGA configuration mode (SER_EN = high) and two-wire ISP programming mode (SER_EN = low). In configuration mode, it delivers stored bitstream directly to FPGA DIN using simple timing-controlled readback; no external controller is required. Write protection is implemented via dedicated WP input (available on AT17LV65/128/256 variants) and programmable block-level locks.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 128 Kbit (131,072 × 1-bit) - sufficient for mid-complexity Xilinx XC4000 or Altera FLEX FPGA configurations |
| Operating voltage | 3.3 V ±10% or 5.0 V ±5% (commercial) / ±10% (industrial) - enables direct integration into mixed-voltage FPGA systems |
| Temperature range | –40°C to +85°C - qualified for industrial-grade embedded control and automation applications |
| Endurance | 100,000 write cycles - supports field firmware updates and reconfiguration without premature wear-out |
| Data retention | 90 years at 85°C - ensures long-term reliability in thermally stressed environments without refresh |
| Max clock frequency | 10 MHz (3.3V industrial), 12.5 MHz (5V commercial) - matches standard FPGA CCLK timing budgets |
| Standby current | 100 µA at 3.3V industrial - minimizes system power during FPGA idle or configuration hold states |
Pinout & Package
AT17LV128-10SI is packaged in a 20-lead SOIC (20S2), 0.300" wide, JEDEC-compliant gull-wing surface-mount package measuring 12.8 mm × 7.5 mm × 2.35 mm. Pin 1 identifier is marked by a beveled corner and notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 | NC (No Connect) | Unbonded pins - must remain unconnected per design; no internal function or pull-up/down |
| 11 | GND | Ground reference for all I/O and core logic; requires local 0.2 µF decoupling to VCC |
| 12 | VCC | Primary power supply input - accepts either 3.3V or 5V with specified tolerance ranges |
| 13 | RESET/OE | Dual-function input: active-low reset (resets address counter) and active-high output enable (controls DATA driver) |
| 14 | CE | Chip Enable (active low) - enables read operations and disables address counter when high (standby mode) |
| 15 | DATA | Three-state bidirectional I/O - outputs configuration bits to FPGA DIN; used as input during ISP programming |
| 16 | CLK | Configuration clock input - increments internal address/bit counter on rising edge; driven by FPGA CCLK |
| 17 | SER_EN | Serial Enable (active high) - must be tied to VCC for FPGA configuration; pulled low to enter two-wire ISP mode |
| 18 | CEO | Chip Enable Output (active low) - signals end-of-data to enable next cascaded EEPROM in daisy chain |
| 19, 20 | NC | No-connect pins - electrically isolated; no routing or termination required |
Key Features
| Feature | Design Value |
|---|---|
| In-system programmability | Two-wire serial interface (SER_EN low) enables field reprogramming without socket removal or UV erasure |
| Cascadable read-back | CEO output allows seamless chaining of multiple AT17LV devices to support larger FPGA bitstreams or multi-device systems |
| Programmable reset polarity | User-configurable RESET/OE logic polarity via internal EEPROM bytes - eliminates need for external inverters in legacy designs |
| Low-power standby | 100 µA max ICCS at 3.3V industrial - reduces system quiescent power while preserving configuration integrity |
| Industrial reliability | 100,000 write cycles and 90-year data retention at 85°C - validated for harsh environments and long-lifecycle deployments |
Applications
| Industrial PLC Configuration | FPGA-Based Motor Control |
|---|---|
Use Scenario: Configuring Xilinx Spartan or Altera MAX II FPGAs in programmable logic controllers deployed in factory-floor automation cabinets. IC Role / Device Role / Timing Role: Serial configuration memory providing deterministic bitstream load at power-up or warm reset; synchronized to FPGA CCLK. Use Value: Enables field-upgradable logic without hardware changes; 90-year data retention ensures firmware persistence across decades of operation. | Use Scenario: Storing motor control algorithms in SRAM-based FPGAs used in servo drives operating under variable thermal loads. IC Role / Device Role / Timing Role: Master-serial mode configurator delivering bitstream to FPGA DIN; CEO output coordinates multi-FPGA synchronization in distributed drive systems. Use Value: Cascading support allows expansion beyond single-device density limits; industrial temp rating (-40°C to +85°C) guarantees startup reliability in unconditioned enclosures. |
| Avionics FPGA Bootloader | Test Equipment Reconfigurable Logic |
Use Scenario: Loading safety-critical configuration data into radiation-tolerant FPGAs within airborne flight control subsystems. IC Role / Device Role / Timing Role: Nonvolatile configuration source with programmable reset polarity to match legacy avionics reset architectures. Use Value: Dual-voltage support (3.3V/5V) simplifies integration into mixed-supply avionics backplanes; 100,000 write cycles allow repeated qualification testing. | Use Scenario: Enabling rapid reconfiguration of FPGA-based digital pattern generators and logic analyzers in automated test equipment (ATE). IC Role / Device Role / Timing Role: In-system programmable EEPROM allowing over-the-air bitstream updates without removing boards from rack-mounted chassis. Use Value: Two-wire ISP eliminates need for JTAG programmers; low standby current (<100 µA) extends battery life in portable ATE units. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FPGA configuration memory applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| Xilinx XC18V02 | 2-Mbit capacity; only 3.3V operation; no 5V support; different pinout and timing (TCK-driven, not CCLK-synchronized) | Designed exclusively for Xilinx Virtex families; lacks cascading CEO output and dual-voltage flexibility | Select when targeting Virtex-4/5 platforms with higher density needs and 3.3V-only infrastructure |
| Microchip (Atmel) AT17LV256-10SI | 256-Kbit capacity; identical pinout, timing, and feature set; same 20-lead SOIC package and industrial temperature rating | Direct upgrade path for designs requiring >128 Kbit configuration storage without PCB layout change | Choose when future FPGA bitstream growth is anticipated; drop-in replacement with doubled memory depth |
Compared with XC18V02 and AT17LV256-10SI, the AT17LV128-10SI offers optimal balance of industrial temperature compliance, dual-voltage support, and cascading capability - making it uniquely suited for heterogeneous FPGA ecosystems where interoperability across Xilinx, Altera, and legacy Atmel platforms is required.
Availability
AT17LV128-10SI is available at Aetrix Electronics and suitable for industrial automation, aerospace avionics, and test equipment requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for AT17LV128-10SI includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology is a global semiconductor company specializing in microcontrollers, analog components, and nonvolatile memory solutions, with deep heritage in FPGA configuration technology via its acquisition of Atmel.
The AT17LV series was originally developed by Atmel to provide cost-effective, pin-compatible configuration memory for SRAM-based FPGAs across Xilinx, Altera, and ORCA platforms - emphasizing industrial reliability, in-system programmability, and seamless master-serial integration.
FAQ
What is the maximum clock frequency supported by AT17LV128-10SI during FPGA configuration?
The AT17LV128-10SI supports up to 10 MHz at 3.3V under industrial conditions (–40°C to +85°C), and 12.5 MHz at 5V under commercial conditions (0°C to +70°C). These values are defined in the AC Characteristics tables and reflect guaranteed timing margins for reliable bitstream delivery to FPGA DIN inputs without setup/hold violations.
Does AT17LV128-10SI support both 3.3V and 5.0V operation simultaneously?
No, AT17LV128-10SI operates at either 3.3V ±10% or 5.0V ±5% (commercial) / ±10% (industrial), but not both simultaneously. The supply voltage must be selected at design time and maintained consistently across VCC and all referenced I/O thresholds. Mixed-voltage signaling is not supported.
Can AT17LV128-10SI be used in a daisy-chain configuration with other AT17LV devices?
Yes, AT17LV128-10SI supports cascading via its CEO (Chip Enable Output) pin, which goes low upon completion of its internal memory read. This signal can drive the CE input of the next AT17LV device in the chain, enabling automatic handoff of configuration data across multiple EEPROMs - a capability confirmed in the device's pin description and cascading application notes.
Is the reset polarity of AT17LV128-10SI fixed or programmable?
The reset polarity of AT17LV128-10SI is programmable. Users can configure the RESET/OE pin to operate as either active-low RESET or active-high OE by programming four specific EEPROM bytes using industry-standard programmers or Atmel's ATDH2225 ISP Cable. This eliminates external logic for polarity adaptation.
What package type does AT17LV128-10SI use, and is it compatible with standard SOIC footprints?
AT17LV128-10SI uses the 20-lead SOIC (20S2) package, a 0.300" wide JEDEC-standard gull-wing surface-mount outline. It is fully compatible with standard 20-lead SOIC footprints and reflow profiles, and shares mechanical dimensions and solder pad requirements with other 20S2 devices - enabling straightforward PCB integration and assembly.
AT17LV128-10SI Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Programmable Type:
- Serial EEPROM
- Memory Size:
- 128kb
- Voltage - Supply:
- 3V ~ 3.6V, 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-SOIC
AT17LV128-10SI FAQ
1.How can I place an order for AT17LV128-10SI through Aetrix?
Please submit a Request for Quotation (RFQ) for AT17LV128-10SI on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT17LV128-10SI reliable?
The price and inventory of AT17LV128-10SI are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT17LV128-10SI is usually 5 days.
3.What payment methods are accepted for AT17LV128-10SI?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT17LV128-10SI transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT17LV128-10SI?
AT17LV128-10SI orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT17LV128-10SI order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT17LV128-10SI?
For technical support, including AT17LV128-10SI datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT17LV128-10SI requirements.
6.How does Aetrix verify that AT17LV128-10SI is sourced from the original manufacturer or authorized distributors?
All AT17LV128-10SI products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT17LV128-10SI meets industry standards.
7.What is the process for return or replacement of AT17LV128-10SI?
All AT17LV128-10SI units undergo pre-shipment inspection (PSI). If there is an issue with AT17LV128-10SI, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT17LV128-10SI part is unused and in its original packaging.
Return procedure for AT17LV128-10SI:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT17LV128-10SI Tags
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