Microchip Technology AT17LV128A-10JC

Overview

AT17LV128A-10JC from Microchip Technology (formerly Atmel) is a 128-Kbit serial FPGA configuration EEPROM designed to store and deliver bitstream data to SRAM-based FPGAs including Altera FLEX® and APEX™, Xilinx Spartan® and Virtex®, and Lucent ORCA® devices. It operates at 3.3V ±10% or 5.0V ±5% (commercial), supports in-system programming via 2-wire bus, and delivers configuration data with 75 ns CLK-to-data delay (3.3V, commercial). Its primary role is master-serial boot memory for FPGA power-up initialization.

For engineers reviewing the AT17LV128A-10JC datasheet, AT17LV128A-10JC pinout, AT17LV128A-10JC application, or AT17LV128A-10JC equivalent, key selection criteria include cascading support via nCASC/nCS daisy-chain, programmable reset polarity, low-power standby current (50 µA at 3.3V), 100,000 write cycles endurance, and compatibility with industry-standard FPGA configuration protocols.

Technical Context

The AT17LV128A-10JC implements a serial-access, address-counter-based configuration memory architecture synchronized to an external DCLK signal. It uses a tri-state DATA output controlled jointly by RESET/OE and nCS, with automatic counter reset on power-up and configurable active-Low/active-High reset polarity programmed into EEPROM bytes.

Cascading is enabled through the open-drain nCASC output, which asserts Low when the internal counter reaches its maximum value (131,072 bits), enabling the next device in a daisy-chain. SER_EN must be held High during FPGA loading and pulled Low only for ISP programming - no external controller is required for master-serial operation.

Key Specifications

Pinout & Package

AT17LV128A-10JC is supplied in a 20-lead Plastic Leaded Chip Carrier (PLCC) package, 9.779 mm × 9.779 mm body, 1.27 mm lead pitch, JEDEC MS-018 compliant. Pin 1 identifier is a corner notch; leads are J-bent with coplanarity ≤0.102 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FPGA configuration memory applications.

Compared with AT17LV256A-10JC and XC18V02PC44C, the AT17LV128A-10JC offers optimal cost and footprint efficiency for mid-density FLEX 6000/8000 and Spartan-II bitstreams, while maintaining full interoperability with Altera, Xilinx, and ORCA ecosystems without protocol translation.

Availability

AT17LV128A-10JC is available at Aetrix Electronics and suitable for industrial PLC configuration, telecom line card boot memory, and medical imaging FPGA initialization requiring stable component supply across extended product lifecycles.

Supply support for AT17LV128A-10JC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology acquired Atmel in 2016 and maintains full support for the legacy AT17LV configuration EEPROM family, providing long-term product availability and technical documentation.

The AT17LV series was engineered specifically for FPGA bitstream storage in master-serial mode, targeting cost-sensitive, high-reliability embedded systems where simplicity, low power, and broad vendor compatibility are critical.

FAQ

What is the function of the SER_EN pin on the AT17LV128A-10JC?

The SER_EN pin on the AT17LV128A-10JC selects operational mode: when held High, it enables standard FPGA configuration mode where DATA and DCLK interface directly with the FPGA; when pulled Low, it activates 2-wire in-system programming mode for reprogramming the EEPROM contents. For normal operation, SER_EN must be tied to VCC - leaving it floating may cause undefined behavior during power-up. The AT17LV128A-10JC requires no external programming hardware when SER_EN is used correctly.

Does the AT17LV128A-10JC support cascading with other configuration EEPROMs?

Yes, the AT17LV128A-10JC supports hardware cascading via its dedicated nCASC output pin, which goes Low when the internal address counter reaches its final bit (131,071). This signal is intended to drive the nCS input of the next AT17LV device in a daisy-chain, enabling seamless expansion beyond 128 Kbit. Cascading preserves timing integrity because each device releases its DATA line before the next begins driving - the AT17LV128A-10JC handles handoff autonomously without FPGA intervention.

What is the maximum clock frequency supported by the AT17LV128A-10JC?

The AT17LV128A-10JC supports a maximum input clock frequency of 10 MHz under commercial conditions (3.3 V ±10%, 0°C to +70°C), as specified in its AC Characteristics table. At 5.0 V ±5%, the maximum clock frequency increases to 12.5 MHz. These limits govern the speed at which the FPGA can clock configuration data from the AT17LV128A-10JC - exceeding them risks data misalignment or incomplete bitstream loading. The AT17LV128A-10JC does not generate its own clock; it relies entirely on the FPGA's DCLK signal.

Can the AT17LV128A-10JC be used with both 3.3 V and 5.0 V FPGAs?

Yes, the AT17LV128A-10JC is explicitly rated for dual-supply operation: 3.3 V ±10% and 5.0 V ±5% (commercial) or ±10% (industrial). Its VIH and VIL thresholds (2.0 V min high, 0.8 V max low) ensure reliable interfacing with both 3.3 V and 5 V logic families. When powered at 3.3 V, it safely drives 5 V-tolerant FPGA inputs; when powered at 5 V, its outputs meet VOH/VOL specs for 3.3 V receivers with appropriate level-shifting or bus-hold design. The AT17LV128A-10JC eliminates need for external voltage translators in mixed-voltage FPGA systems.

How is reset polarity configured on the AT17LV128A-10JC?

Reset polarity on the AT17LV128A-10JC is user-programmable via four dedicated EEPROM bytes and persists across power cycles. By default, RESET/OE is active-Low for reset and active-High for output enable - matching Altera FLEX® requirements. During programming (via SER_EN Low mode), the polarity can be changed to active-High reset/active-Low OE for Xilinx or ORCA compatibility. This eliminates board-level jumpers or logic inverters; the AT17LV128A-10JC stores the setting internally and applies it automatically on every power-up.