Microchip Technology AT24C02BN-SH-T
- Part No.:
- AT24C02BN-SH-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
AT24C02BN-SH-T.pdf
- Description:
- IC EEPROM 2KBIT I2C 1MHZ 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C02BN-SH-T from Microchip Technology (formerly Atmel) is a 2 Kbit (256 × 8) two-wire serial EEPROM with 1.8 V to 5.5 V operation, 400 kHz I²C interface at 1.8 V, hardware write protection via WP pin, and 1 million write cycles endurance. It serves as nonvolatile configuration storage in embedded systems requiring low-power, space-constrained data retention - e.g., set-top box firmware parameter backup.
For engineers reviewing the AT24C02BN-SH-T datasheet, AT24C02BN-SH-T pinout, AT24C02BN-SH-T application, or AT24C02BN-SH-T equivalent, key selection criteria include its SOIC-8 package with NiPdAu lead finish, 8-byte page write capability, Schmitt-triggered SCL/SDA inputs for noise immunity, and guaranteed 100-year data retention at +85°C.
Technical Context
The AT24C02BN-SH-T implements a standard I²C-compatible two-wire interface with open-drain SDA and edge-triggered SCL, supporting up to eight devices on one bus via hardwired A0–A2 address pins. Its internal architecture includes a 32-page × 8-byte memory array, auto-incrementing address counter, and high-voltage pump for byte/page write operations.
Write protection is enforced by the WP pin: tied to VCC, it locks the full 2 Kbit array; tied to GND, full read/write access is enabled. The device enters standby mode after STOP condition or power-up, drawing ≤3.0 µA at 1.8 V, and uses acknowledge polling to signal write completion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 2048 bits (256 words × 8 bits), organized as 32 pages of 8 bytes each - enables compact firmware parameter storage without external address latches. |
| Interface | Two-wire I²C-compatible serial bus - requires only SCL and SDA lines, compatible with microcontrollers lacking dedicated SPI peripherals. |
| Operating Voltage | 1.8 V to 5.5 V - supports direct interfacing with 1.8 V logic, 3.3 V MCU I/O, and 5 V legacy systems without level shifters. |
| Max Clock Frequency | 400 kHz at 1.8 V / 2.5 V / 2.7 V; 1 MHz at 5 V - ensures deterministic timing margins in noise-prone industrial environments. |
| Write Endurance | 1 million write cycles per byte - sufficient for daily calibration updates over 27 years in field-deployed sensors. |
| Data Retention | 100 years at +85°C - guarantees long-term integrity of stored calibration coefficients or security keys in unpowered equipment. |
| Standby Current | 0.6 µA typical at 1.8 V - minimizes battery drain in always-on IoT nodes powered by coin cells. |
Pinout & Package
AT24C02BN-SH-T is supplied in an 8-lead JEDEC SOIC package (package code 8S1), 0.150" wide body, with NiPdAu lead finish for enhanced solderability and corrosion resistance. Pin 1 is marked by a dot in the top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Device Address Input | Hardwired input determining LSB of 7-bit I²C slave address; enables up to eight AT24C02BN-SH-T devices on one bus. |
| A1 | Device Address Input | Second bit of device address; combined with A0 and A2, selects unique I²C address within 0x50–0x57 range. |
| A2 | Device Address Input | MSB of device address; all three pins must match wiring to ensure correct addressing during multi-device reads/writes. |
| GND | Ground Reference | Return path for VCC and I/O signals; must be low-impedance to maintain noise margin on SCL/SDA lines. |
| VCC | Power Supply | 1.8–5.5 V supply input; decoupling capacitor (0.1 µF) required within 1 cm to suppress switching transients. |
| WP | Write Protect Control | Active-high hardware lock: tied to VCC disables all writes; tied to GND enables full read/write access. |
| SCL | Serial Clock Input | Positive-edge clock for data sampling; Schmitt-trigger input rejects <50 ns noise pulses per AC spec. |
| SDA | Serial Data I/O | Open-drain bidirectional line; requires external pull-up (typically 4.7 kΩ) to VCC for proper I²C bus operation. |
Key Features
| Feature | Design Value |
|---|---|
| Low-voltage operation | Functional down to 1.8 V supply - eliminates need for voltage regulators in 2-cell Li-ion or energy-harvesting designs. |
| Page write capability | 8-byte atomic page writes - reduces firmware update time by 8× vs. byte-by-byte writes, minimizing bus occupancy. |
| Noise-immune inputs | Schmitt-trigger + filtering on SCL/SDA - sustains reliable communication in motor-drive or RF-noisy enclosures. |
| Hardware write protection | WP pin directly gates internal write logic - prevents accidental overwrites during power brownouts or firmware glitches. |
| Lead-free/halogen-free | RoHS-compliant NiPdAu finish and packaging - meets IPC-J-STD-020 moisture sensitivity level 3 (MSL3) requirements. |
Applications
| Industrial Sensor Calibration | Consumer Remote Control ID Storage |
|---|---|
Use Scenario: Storing factory-calibrated temperature offset values and linearization coefficients in a wireless environmental sensor node. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding persistent sensor metadata accessed at boot by the host MCU. Use Value: Enables field-replaceable sensor modules with pre-loaded calibration; eliminates reprogramming step during assembly. |
Use Scenario: Retaining unique IR remote ID codes and user-programmed button mappings across battery removal in smart home remotes. IC Role / Device Role / Timing Role: Low-power serial configuration store accessed only during initialization or user setup mode. Use Value: Preserves personalized settings without requiring cloud sync or manual reconfiguration after battery replacement. |
| POS Terminal Firmware Backup | Medical Device Usage Logs |
Use Scenario: Backing up critical transaction firmware patches and tax table versions in point-of-sale terminals subject to frequent power cycling. IC Role / Device Role / Timing Role: Fail-safe firmware parameter vault updated only during secure OTA updates, not runtime. Use Value: Guarantees rollback to last-known-good firmware after corrupted update, meeting PCI PTS v6.0 reliability requirements. |
Use Scenario: Recording cumulative usage hours, self-test results, and calibration timestamps in portable ultrasound probes. IC Role / Device Role / Timing Role: Tamper-resistant audit trail storage with write-protection enabled during normal operation. Use Value: Supports FDA 21 CFR Part 11 compliance by preventing unauthorized log modification while enabling traceable service history. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| M24C02-RMN6TP | STMicroelectronics 2 Kbit EEPROM; identical 8-lead SOIC package, same 1.8–5.5 V range and 400 kHz speed, but uses different A0–A2 address mapping logic. | Requires verification of I²C address compatibility in multi-device systems due to alternate device address decoding. | Select when sourcing from ST distribution channels; validate address collision behavior before board-level integration. |
| BR24G02NUX-10 | Rohm 2 Kbit EEPROM; same SOIC-8 footprint and NiPdAu finish, but rated for automotive AEC-Q100 Grade 2 (–40°C to +105°C) and offers faster 1 MHz write at 2.5 V. | Supports extended temperature operation and higher-speed writes - suitable for under-hood automotive modules. | Choose for automotive-grade reliability; note BR24G02NUX-10 requires separate WP pin handling per its datasheet revision. |
Compared with AT24C02BN-SH-T, M24C02-RMN6TP offers identical form-factor and voltage range but demands address-map validation, while BR24G02NUX-10 provides automotive qualification and faster write timing at the cost of slightly higher standby current (1.0 µA vs. 0.6 µA at 1.8 V).
Availability
AT24C02BN-SH-T is available at Aetrix Electronics and suitable for industrial sensor calibration, consumer remote control ID storage, POS terminal firmware backup, and medical device usage logs requiring stable component supply across multi-year production cycles.
Supply support for AT24C02BN-SH-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and now manufactures the AT24C02BN-SH-T as part of its broad serial EEPROM portfolio, emphasizing industrial reliability and long-term supply assurance.
This device belongs to the AT24Cxx family of I²C-compatible EEPROMs designed for low-power, space-constrained nonvolatile data storage in embedded control, instrumentation, and consumer electronics.
FAQ
What is the maximum I²C clock frequency supported by the AT24C02BN-SH-T at 1.8 V operation?
The AT24C02BN-SH-T supports a maximum I²C clock frequency of 400 kHz when operating at 1.8 V, 2.5 V, or 2.7 V. This is specified in Table 2-3 of the official datasheet under AC Characteristics. At 5.0 V, the device supports up to 1 MHz. The 400 kHz limit at low voltage ensures robust timing margins for noise immunity and signal integrity in battery-powered applications where AT24C02BN-SH-T is commonly deployed.
Does the AT24C02BN-SH-T require external pull-up resistors on SCL and SDA lines?
Yes, the AT24C02BN-SH-T requires external pull-up resistors on both SCL and SDA lines because its SDA pin is open-drain and SCL is a CMOS input. A typical value is 4.7 kΩ to VCC, selected based on bus capacitance and desired rise time. Without pull-ups, the AT24C02BN-SH-T cannot drive the bus high, resulting in communication failure. This requirement is explicitly stated in the "Bus Timing" and "Pin Description" sections of the AT24C02BN-SH-T datasheet.
How does the Write Protect (WP) pin function on the AT24C02BN-SH-T?
On the AT24C02BN-SH-T, the WP pin is an active-high hardware lock: when connected to VCC, it disables all write operations to the entire 2 Kbit memory array; when tied to GND, full read and write access is enabled. This behavior is confirmed in Table 1-1 ("Write Protect") and Section 1 ("Pin Description") of the datasheet. The AT24C02BN-SH-T does not support partial-array protection - WP asserts globally across all addresses.
What package type and lead finish does the AT24C02BN-SH-T use?
The AT24C02BN-SH-T uses an 8-lead JEDEC SOIC package (package code 8S1) with NiPdAu (Nickel-Palladium-Gold) lead finish. This is explicitly defined in the "Ordering Information" table on page 13 of the datasheet, where "AT24C02BN-SH-T(2) (NiPdAu Lead Finish)" maps to package 8S1. The NiPdAu finish improves solder joint reliability and mitigates intermetallic growth compared to standard SnPb or pure Sn finishes.
Can the AT24C02BN-SH-T be used in automotive applications?
The AT24C02BN-SH-T is rated for industrial temperature range (–40°C to +85°C) and is not qualified to AEC-Q100 automotive standards. While it may function in some benign automotive environments, Microchip's official documentation states that "Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life." For automotive use, designers should select automotive-qualified alternatives such as the BR24G02NUX-10 or Microchip's own AEC-Q100-certified EEPROMs instead of the AT24C02BN-SH-T.
AT24C02BN-SH-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 2Kbit
- Memory Organization:
- 256 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
AT24C02BN-SH-T FAQ
1.How can I place an order for AT24C02BN-SH-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C02BN-SH-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C02BN-SH-T reliable?
The price and inventory of AT24C02BN-SH-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C02BN-SH-T is usually 5 days.
3.What payment methods are accepted for AT24C02BN-SH-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C02BN-SH-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C02BN-SH-T?
AT24C02BN-SH-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C02BN-SH-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C02BN-SH-T?
For technical support, including AT24C02BN-SH-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C02BN-SH-T requirements.
6.How does Aetrix verify that AT24C02BN-SH-T is sourced from the original manufacturer or authorized distributors?
All AT24C02BN-SH-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C02BN-SH-T meets industry standards.
7.What is the process for return or replacement of AT24C02BN-SH-T?
All AT24C02BN-SH-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C02BN-SH-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C02BN-SH-T part is unused and in its original packaging.
Return procedure for AT24C02BN-SH-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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