Microchip Technology AT24C04C-MAHM-T
- Part No.:
- AT24C04C-MAHM-T
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT24C04C-MAHM-T.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C04C-MAHM-T from Microchip Technology is a 4-Kbit I²C-compatible serial EEPROM organized as 512 × 8 bits, operating from 1.7V to 5.5V with industrial temperature range (−40°C to +85°C), 1 MHz Fast Mode Plus support at ≥2.5V, and hardware write-protection via dedicated WP pin - used for nonvolatile configuration storage in embedded controllers and power management systems.
For engineers reviewing the AT24C04C-MAHM-T datasheet, AT24C04C-MAHM-T pinout, AT24C04C-MAHM-T application, or AT24C04C-MAHM-T equivalent, key selection criteria include I²C bus voltage compatibility (1.7–5.5V), page-write timing (≤5 ms), standby current (≤6 μA), and 8-pad UDFN package footprint constraints.
Technical Context
The AT24C04C-MAHM-T implements a two-wire I²C interface with Schmitt-triggered, noise-filtered SDA/SCL inputs and an internal pull-down bias on A1/A2/WP pins. It supports Standard (100 kHz), Fast (400 kHz), and Fast Mode Plus (1 MHz) clock rates depending on VCC level.
Memory is organized into 32 pages of 16 bytes each, enabling partial-page writes and supporting random/sequential read modes. Write protection is implemented via hardware-level WP pin control, with full-array lockout when WP = VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4,096 bits (512 × 8), sufficient for firmware configuration, calibration data, or device ID storage in space-constrained designs |
| Supply Voltage Range | 1.7V to 5.5V - enables direct interfacing with 1.8V, 3.3V, and 5V microcontrollers without level shifting |
| Max Clock Frequency | 1 MHz (Fast Mode Plus) at VCC ≥ 2.5V - reduces EEPROM access latency in time-critical boot or initialization sequences |
| Write Cycle Time | ≤5 ms maximum - defines worst-case delay before host can resume bus activity after a write command |
| Standby Current | ≤6 μA at VCC = 5.5V - critical for battery-powered devices requiring ultra-low quiescent power during sleep |
| Endurance & Retention | 1,000,000 write cycles / 100-year data retention at 55°C - ensures long-term reliability in industrial logging or metering applications |
| ESD Protection | >4,000V HBM - provides robustness against handling and system-level ESD events without external protection |
Pinout & Package
AT24C04C-MAHM-T is housed in an 8-pad UDFN (Ultra Thin Dual Flat No-lead) package with wettable flanks, measuring 2.0 mm × 1.6 mm × 0.55 mm, optimized for automated optical inspection (AOI) and high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (NC) | No Connect | Unbonded die pad; must be left floating or tied to GND per layout guidelines - no electrical function |
| 2 (A1) | Device Address Input | Hardwired to GND/VCC to set LSB of 7-bit I²C address; enables up to four AT24C04C devices on same bus |
| 3 (A2) | Device Address Input | Hardwired to GND/VCC to set second LSB of I²C address; works with A1 to configure unique slave address |
| 4 (GND) | Ground Reference | Primary return path for VCC and I/O currents; requires low-impedance connection to system ground plane |
| 5 (SDA) | Serial Data I/O | Open-drain bidirectional line; requires external pull-up resistor (≤10 kΩ); supports wire-OR with other I²C devices |
| 6 (SCL) | Serial Clock Input | Input-only clock line; rising edge latches input data, falling edge outputs data; must be pulled high externally |
| 7 (WP) | Write-Protect Control | Hardware lock: tied to VCC disables all writes; tied to GND enables full memory access; internally pulled down if floating |
| 8 (VCC) | Power Supply | Single supply rail powering logic and EEPROM array; must ramp monotonically at ≤0.1 V/µs during power-up |
Key Features
| Feature | Design Value |
|---|---|
| 16-byte page write mode | Enables efficient burst writes without crossing page boundaries - reduces total write time vs. byte-by-byte programming |
| Schmitt-triggered, filtered inputs | Rejects noise spikes ≤100 ns (Fast Mode) or ≤50 ns (Fast Mode Plus), improving I²C bus reliability in electrically noisy environments |
| Internal power-on reset (POR) | Prevents spurious writes during power ramp-up; requires ≥100 µs stabilization before first command after VCC reaches stable level |
| Green RoHS-compliant packaging | Lead-free, halide-free UDFN package meets IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL1) requirements |
| Software reset capability | Recovers from bus hang via ≤9 dummy SCL clocks - avoids mandatory power cycle in field-deployed systems |
Applications
| Industrial Sensor Calibration | Smart Meter Configuration Storage |
|---|---|
|
Use Scenario: Storing factory-calibrated sensor offset/gain coefficients and temperature compensation tables in environmental monitoring nodes. IC Role / Device Role / Timing Role: Nonvolatile configuration register holding persistent calibration parameters accessed during sensor initialization. Use Value: Enables field-replaceable sensors with zero recalibration; leverages 100-year data retention and 1M-cycle endurance for lifetime accuracy. |
Use Scenario: Retaining tariff schedules, billing history, and communication module settings in utility-grade electricity meters. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store updated infrequently but requiring guaranteed persistence across decades. Use Value: WP pin hardware lock prevents unauthorized firmware or tariff changes; 4Kbit capacity accommodates multiple tariff zones and audit logs. |
| Embedded Controller Boot Configuration | IoT Edge Device Identity Management |
|
Use Scenario: Holding bootloader configuration flags (e.g., safe mode enable, UART debug port state, watchdog timeout) in industrial PLCs. IC Role / Device Role / Timing Role: Early-boot configuration source read before main application starts - accessed via I²C during cold start. Use Value: Low 1.7V operation allows reading before full 3.3V rail stabilizes; ≤5 ms write cycle enables dynamic flag updates during diagnostics. |
Use Scenario: Storing device-specific cryptographic keys, MAC addresses, and certificate fingerprints in battery-powered asset trackers. IC Role / Device Role / Timing Role: Secure identity vault isolated from main MCU flash - accessed only during secure boot or TLS handshake. Use Value: 6 μA standby current extends 10-year battery life; write-protection prevents key overwrite during OTA updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AT24C04D-MAHM-T | Successor revision with enhanced ESD (>6 kV HBM) and extended AC timing margin at 1.7V; identical pinout and memory map | Preferred for new designs targeting higher robustness in harsh ESD environments (e.g., factory automation panels) | Select AT24C04D-MAHM-T if long-term supply continuity and improved noise immunity are prioritized over legacy qualification. |
| M24C04-RMN6TP | 4-Kbit I²C EEPROM from STMicroelectronics; same 1.7–5.5V range and 8-pin UDFN package, but slower max clock (400 kHz only) | Suitable where bus speed < 400 kHz suffices and multi-source procurement is required for supply chain diversification | Choose M24C04-RMN6TP when dual-sourcing is mandated and Fast Mode Plus (1 MHz) is not needed. |
Compared with AT24C04C-MAHM-T, the AT24C04D-MAHM-T offers verified ESD improvement without layout or firmware changes, while M24C04-RMN6TP provides second-source assurance at the cost of reduced bus throughput - both require validation of WP pin behavior and power-up timing in target systems.
Availability
AT24C04C-MAHM-T is available at Aetrix Electronics and suitable for industrial sensor nodes, smart metering systems, and embedded controller boot configurations requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for AT24C04C-MAHM-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a global semiconductor company specializing in microcontrollers, analog components, and memory solutions, with a focus on reliability, longevity, and industrial-grade qualification.
The AT24C04C-MAHM-T belongs to Microchip's serial EEPROM product line, designed specifically for low-voltage, low-power nonvolatile storage in space-constrained embedded systems requiring I²C interface simplicity and long-term data integrity.
FAQ
What is the maximum I²C clock frequency supported by the AT24C04C-MAHM-T?
The AT24C04C-MAHM-T supports up to 1 MHz (Fast Mode Plus) when VCC is 2.5V or higher. At 1.7V–2.5V, the maximum clock rate is 400 kHz (Fast Mode). Standard Mode (100 kHz) operates across the full 1.7V–5.5V range. These limits are defined by AC timing specifications in DS20006127B, and exceeding them may cause communication failures or data corruption in the AT24C04C-MAHM-T.
Does the AT24C04C-MAHM-T require external pull-up resistors on SDA and SCL lines?
Yes, the AT24C04C-MAHM-T requires external pull-up resistors on both SDA and SCL lines because SDA is open-drain and SCL is input-only. Recommended values are ≤10 kΩ for SDA (to meet VOL specs under load) and ≤4 kΩ for 400 kHz operation or ≤1.3 kΩ for 1 MHz - per Table 4-3 in the AT24C04C-MAHM-T datasheet. Failure to install appropriate pull-ups will prevent reliable I²C communication.
How does the write-protect (WP) pin function on the AT24C04C-MAHM-T?
When the WP pin of the AT24C04C-MAHM-T is driven to VCC, all write operations (byte, page, or erase) to the entire memory array are inhibited. When WP is at GND, normal write functionality is enabled. If left floating, WP is internally pulled down to GND, enabling writes - but Microchip recommends hardwiring WP to a known state to avoid noise-induced glitches that could unintentionally lock memory during operation of the AT24C04C-MAHM-T.
What is the memory organization of the AT24C04C-MAHM-T?
The AT24C04C-MAHM-T organizes its 4,096 bits as 512 words of 8 bits each, grouped into 32 pages of 16 bytes. This structure enables efficient 16-byte page writes without crossing page boundaries. The page architecture directly impacts write timing: a single page write completes within 5 ms, while multi-page writes require sequential commands - a key constraint reflected in firmware design for the AT24C04C-MAHM-T.
Is the AT24C04C-MAHM-T compatible with 1.8V microcontrollers?
Yes, the AT24C04C-MAHM-T is fully compatible with 1.8V microcontrollers: it operates down to 1.7V VCC, supports I²C Standard and Fast Modes at 1.7V–5.5V, and features input thresholds (VIL ≤ 0.3×VCC, VIH ≥ 0.7×VCC) that align with 1.8V logic levels. Its 8-pad UDFN package also matches common 1.8V SoC footprints, making the AT24C04C-MAHM-T a drop-in solution for low-voltage embedded systems.
AT24C04C-MAHM-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 550 ns
- Voltage - Supply:
- 1.7V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT24C04C-MAHM-T FAQ
1.How can I place an order for AT24C04C-MAHM-T through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C04C-MAHM-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C04C-MAHM-T reliable?
The price and inventory of AT24C04C-MAHM-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C04C-MAHM-T is usually 5 days.
3.What payment methods are accepted for AT24C04C-MAHM-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C04C-MAHM-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C04C-MAHM-T?
AT24C04C-MAHM-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C04C-MAHM-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C04C-MAHM-T?
For technical support, including AT24C04C-MAHM-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C04C-MAHM-T requirements.
6.How does Aetrix verify that AT24C04C-MAHM-T is sourced from the original manufacturer or authorized distributors?
All AT24C04C-MAHM-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C04C-MAHM-T meets industry standards.
7.What is the process for return or replacement of AT24C04C-MAHM-T?
All AT24C04C-MAHM-T units undergo pre-shipment inspection (PSI). If there is an issue with AT24C04C-MAHM-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C04C-MAHM-T part is unused and in its original packaging.
Return procedure for AT24C04C-MAHM-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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