My Inquiry
My Account
Microchip Technology AT24C04C-STPD-TVAO
- Part No.:
- AT24C04C-STPD-TVAO
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- SOT-23-5 Thin, TSOT-23-5
- Datasheet:
-
AT24C04C-STPD-TVAO.pdf
- Description:
- IC EEPROM 4KBIT I2C TSOT23-5
- Quantity:
- Payment:
- Shipping:
Inventory:4,276
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
AT24C04C-STPD-TVAO from Microchip Technology (acquired Atmel) is a 4-kilobit automotive-grade serial EEPROM organized as 512 words × 8 bits, supporting I²C-compatible 2-wire interface at up to 400 kHz, with hardware write protection via WP pin and 16-byte page write capability. It operates from 2.5V to 5.5V across -40°C to +125°C (Grade 1), targeting infotainment configuration storage, ADAS sensor calibration data retention, and ECU parameter backup in passenger vehicles.
For engineers reviewing the AT24C04C-STPD-TVAO datasheet, AT24C04C-STPD-TVAO pinout, AT24C04C-STPD-TVAO application, or AT24C04C-STPD-TVAO equivalent, key selection criteria include Grade 1 AEC-Q100 qualification, 16-byte page write mode, Schmitt-triggered noise-immune inputs, self-timed 5 ms max write cycle, and compatibility with 1.7–5.5 V systems when used in Grade 3 variants.
Technical Context
The AT24C04C-STPD-TVAO implements a dedicated I²C slave interface with fixed 7-bit device address prefix '1010', using A2 and A1 pins for hardwired addressing (A0 is NC). Its internal memory array is segmented into 32 pages of 16 bytes each, requiring a 9-bit word address for random access.
Write operations support both byte and 16-byte page modes, with automatic address roll-over within page boundaries; read operations include current-address, random-address, and sequential modes-all synchronized to SCL edges with ACK/NACK protocol. The device enters low-power standby after Stop condition or power-up, drawing ≤6.0 µA at 5.0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4,096 bits (512 × 8), enabling storage of firmware flags, trim values, or small configuration tables |
| Interface | I²C-compatible 2-wire serial bus, compatible with standard microcontroller I²C peripherals without protocol translation |
| Max Clock Frequency | 400 kHz at VCC = 2.5 V, supporting real-time parameter updates in fast-boot automotive subsystems |
| Write Cycle Time | 5 ms maximum self-timed write, allowing deterministic timing budgeting for critical save operations |
| Endurance & Retention | 1,000,000 write cycles and 100-year data retention, validated for lifetime use in unattended vehicle modules |
| Operating Voltage | 2.5 V to 5.5 V (Grade 1), matching typical automotive MCU I/O rail ranges without level-shifting |
| Temperature Range | -40°C to +125°C per AEC-Q100 Grade 1, qualified for under-hood and cockpit-adjacent placement |
Pinout & Package
AT24C04C-STPD-TVAO is supplied in an 8-lead JEDEC SOIC package (8S1), 0.150" wide, with gull-wing leads and NiPdAu lead finish. Pin 1 is marked by a beveled corner or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A0 | Address Input (No Connect) | Not connected internally; must be left floating or tied to GND/VCC-no effect on device addressing |
| A1 | Device Address Input | Hardwired bit for I²C slave address; enables up to four AT24C04C devices on same bus |
| A2 | Device Address Input | MSB of 2-bit address; combined with A1, selects one of four possible device addresses (1010xx0) |
| GND | Ground Reference | System return path for VCC and signal logic; requires low-impedance connection to minimize noise coupling |
| VCC | Power Supply | 2.5–5.5 V supply input; decoupling capacitor (0.1 µF ceramic) required within 10 mm of pin |
| WP | Write Protect Control | Active-high hardware lock: tied to VCC disables all writes; tied to GND enables full read/write access |
| SCL | Serial Clock Input | Positive-edge sampled clock; open-drain compatible; requires external pull-up resistor (1.3 kΩ @ 2.5 V) |
| SDA | Serial Data I/O | Bi-directional open-drain bus line; shared with other I²C devices; requires same pull-up as SCL |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Enables robust operation in noisy automotive environments by rejecting sub-threshold voltage transients on SCL/SDA |
| 16-byte page write mode | Reduces I²C transaction overhead by up to 15× vs. byte writes-critical for burst calibration data logging |
| Hardware write protection (WP) | Prevents accidental overwrites during power brownouts or firmware glitches without software intervention |
| AEC-Q100 Grade 1 qualification | Validated for continuous operation at 125°C ambient, meeting reliability requirements for safety-critical ECUs |
| Low standby current (≤6.0 µA) | Minimizes battery drain in always-on vehicle modules such as telematics or keyless entry receivers |
Applications
| Infotainment System Configuration Storage | ADAS Sensor Calibration Data Retention |
|---|---|
Use Scenario: Storing user preferences (volume, display brightness, language), radio presets, and Bluetooth pairing IDs across power cycles in head units. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed via I²C during boot and runtime; no timing-critical latency constraints. Use Value: Enables instant UI restoration without reconfiguration; leverages 100-year data retention to outlive vehicle service life. | Use Scenario: Saving factory-calibrated offset/gain coefficients for radar or camera sensors after production-line alignment. IC Role / Device Role / Timing Role: Write-once-after-calibration, read-frequently storage element; accessed during sensor initialization sequence. Use Value: Eliminates need for external calibration jigs in field service; ensures consistent sensor performance across temperature and aging. |
| Engine Control Unit (ECU) Trim Parameter Backup | Body Control Module (BCM) Fault Log Archiving |
Use Scenario: Backing up adaptive fuel trim values learned during closed-loop operation to survive ECU reset or battery disconnect. IC Role / Device Role / Timing Role: High-reliability shadow memory updated periodically during idle; accessed at engine start. Use Value: Reduces cold-start emissions and improves drivability by restoring learned corrections within 200 ms of ignition. | Use Scenario: Recording diagnostic trouble codes (DTCs), event timestamps, and module voltage anomalies over extended vehicle uptime. IC Role / Device Role / Timing Role: Sequential-write buffer with circular overwrite policy; written asynchronously during CAN message processing. Use Value: Supports ISO 14229 UDS services for technician diagnostics without requiring external flash or SRAM expansion. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STMicroelectronics M24C04-RMN6TP | Same 4K density, I²C interface, and SOIC-8 package; rated for -40°C to +105°C (Grade 2), not Grade 1 | Limited to cabin-mounted modules; unsuitable for under-hood deployment above 105°C | Select when cost sensitivity outweighs extended temperature requirement and AEC-Q100 Grade 1 is not mandated |
| Rohm BR24G04FJ-WE2 | 4K I²C EEPROM in TSSOP-8; supports 1.7–5.5 V, -40°C to +105°C; includes software write protection in addition to WP pin | Requires PCB layout change due to different footprint; software lock adds flexibility but increases firmware complexity | Choose for space-constrained designs needing TSSOP and dual-layer write security |
Compared with M24C04-RMN6TP and BR24G04FJ-WE2, AT24C04C-STPD-TVAO uniquely delivers AEC-Q100 Grade 1 qualification in SOIC-8 with proven 125°C operation-critical for powertrain and chassis control nodes where thermal margin is non-negotiable.
Availability
AT24C04C-STPD-TVAO is available at Aetrix Electronics and suitable for automotive infotainment, ADAS calibration, and ECU parameter backup requiring stable component supply across extended temperature and long product lifecycles.
Supply support for AT24C04C-STPD-TVAO includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full ownership of the AT24CxxC EEPROM family, delivering high-reliability nonvolatile memory solutions for automotive, industrial, and computing markets.
The AT24C04C belongs to Microchip's automotive-qualified serial EEPROM product line, engineered specifically for robust data retention in harsh electrical and thermal environments found in modern vehicles-including start-stop systems and electrified powertrains.
FAQ
What is the memory organization of the AT24C04C-STPD-TVAO?
The AT24C04C-STPD-TVAO contains 4,096 bits of EEPROM memory organized as 512 words × 8 bits, internally segmented into 32 pages of 16 bytes each. This structure supports efficient 16-byte page writes and requires a 9-bit word address for random access. The device uses A2 and A1 pins for hardwired I²C addressing, while A0 is not connected-confirmed in Section 4 (Pin Description) and Table 5-1 (Memory Organization) of the official datasheet.
Does the AT24C04C-STPD-TVAO support 1.8 V operation?
No, the AT24C04C-STPD-TVAO is specified for Grade 1 operation only, with a minimum supply voltage of 2.5 V. It does not support 1.8 V or 1.7 V operation. For 1.7–5.5 V compatibility, Microchip offers Grade 3 variants such as AT24C04C-SS9M-T, which carry different ordering codes and temperature ratings. The STPD suffix explicitly denotes 2.5–5.5 V Grade 1 qualification.
How many AT24C04C-STPD-TVAO devices can share the same I²C bus?
Up to four AT24C04C-STPD-TVAO devices can coexist on a single I²C bus. This is enabled by the two hardwired address pins A2 and A1, which combine with the fixed '1010' prefix to form a 4-bit device address (e.g., 1010000, 1010001, 1010010, 1010011). A0 is not connected and plays no role in addressing-verified in Section 7 (Device Addressing) and Figure 7-1 of the datasheet.
What is the purpose of the WP pin on the AT24C04C-STPD-TVAO?
The WP (Write Protect) pin on the AT24C04C-STPD-TVAO provides hardware-level write inhibition: when pulled high to VCC, it disables all write operations-including byte, page, and erase-across the entire memory array. When grounded, full read/write functionality is restored. This feature prevents corruption during power instability or firmware faults and is independent of software commands-detailed in Section 4 (Pin Description) and Figure 4-1 (Write Protect).
Is the AT24C04C-STPD-TVAO RoHS and AEC-Q100 compliant?
Yes, the AT24C04C-STPD-TVAO is RoHS-compliant (lead-free, halogen-free) and qualified to AEC-Q100 Grade 1 standards for automotive use, with operating temperature range -40°C to +125°C. The 'P' in the package code 'STPD' explicitly denotes Automotive Grade 1, and the NiPdAu lead finish meets J-STD-020 moisture sensitivity and solderability requirements-confirmed in Section 11.2.1 (Ordering Code Information) and Package Marking Table 11.3.
AT24C04C-STPD-TVAO Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- SOT-23-5 Thin, TSOT-23-5
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 450 ns
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- TSOT-23-5
AT24C04C-STPD-TVAO FAQ
1.How can I place an order for AT24C04C-STPD-TVAO through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C04C-STPD-TVAO on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C04C-STPD-TVAO reliable?
The price and inventory of AT24C04C-STPD-TVAO are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C04C-STPD-TVAO is usually 5 days.
3.What payment methods are accepted for AT24C04C-STPD-TVAO?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C04C-STPD-TVAO transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C04C-STPD-TVAO?
AT24C04C-STPD-TVAO orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C04C-STPD-TVAO order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C04C-STPD-TVAO?
For technical support, including AT24C04C-STPD-TVAO datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C04C-STPD-TVAO requirements.
6.How does Aetrix verify that AT24C04C-STPD-TVAO is sourced from the original manufacturer or authorized distributors?
All AT24C04C-STPD-TVAO products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C04C-STPD-TVAO meets industry standards.
7.What is the process for return or replacement of AT24C04C-STPD-TVAO?
All AT24C04C-STPD-TVAO units undergo pre-shipment inspection (PSI). If there is an issue with AT24C04C-STPD-TVAO, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C04C-STPD-TVAO part is unused and in its original packaging.
Return procedure for AT24C04C-STPD-TVAO:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
AT24C04C-STPD-TVAO Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
