Microchip Technology AT24C04C-XHM-T

Overview

AT24C04C-XHM-T from Microchip Technology is a 4-Kbit I²C-compatible serial EEPROM organized as 512 × 8 bits, operating from 1.7V to 5.5V with industrial temperature range (−40°C to +85°C), 1 MHz Fast Mode Plus support at ≥2.5V, and hardware write-protection via WP pin - used for configuration storage in embedded controllers, power management units, and sensor calibration modules.

For engineers reviewing the AT24C04C-XHM-T datasheet, AT24C04C-XHM-T pinout, AT24C04C-XHM-T application, or AT24C04C-XHM-T equivalent, key selection considerations include I²C bus voltage compatibility (1.7–5.5V), page-write timing (≤5 ms), standby current (≤6 μA), and A1/A2 address pin configuration for multi-device bus topology.

Technical Context

The AT24C04C-XHM-T implements a two-wire I²C interface with Schmitt-triggered, noise-filtered SDA/SCL inputs and open-drain bidirectional data transfer. It supports Standard (100 kHz), Fast (400 kHz), and Fast Mode Plus (1 MHz) speeds depending on VCC level, with automatic ACK/NACK handshaking and 9-cycle per-byte protocol timing.

Internally, it uses a high-voltage generation circuit for EEPROM programming, a hardware address comparator for device selection (A1/A2 pins), and a power-on reset (POR) circuit with 100 µs tPUP delay. Write protection is implemented via dedicated WP pin tied to VCC or GND, with internal pull-down when floating.

Key Specifications

Pinout & Package

AT24C04C-XHM-T is housed in an 8-pad UDFN package (2.0 mm × 1.6 mm, 0.5 mm pitch) with wettable flanks, RoHS-compliant and halide-free. The exposed pad is optional and may be connected to GND or left floating.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with AT24C04D-XHM-T, the AT24C04C-XHM-T offers identical functionality and pinout but lacks the enhanced ESD rating and marginally faster write cycle; versus M24C04-RMN6TP, it delivers superior speed, smaller footprint, and broader voltage compatibility - making it optimal for next-generation compact, high-speed embedded systems.

Availability

AT24C04C-XHM-T is available at Aetrix Electronics and suitable for industrial sensor calibration, embedded power management units, and medical device configuration vaults requiring stable component supply, long-lifecycle assurance, and RoHS-compliant sourcing.

Supply support for AT24C04C-XHM-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a global provider of microcontrollers, analog, FPGA, and memory solutions, with focus on embedded control, connectivity, and security.

The AT24C04C belongs to Microchip's serial EEPROM product line, designed specifically for reliable, low-power, I²C-based nonvolatile storage in space-constrained industrial, automotive, and medical applications.

FAQ

What is the maximum I²C clock frequency supported by the AT24C04C-XHM-T?

The AT24C04C-XHM-T supports 100 kHz in Standard mode (1.7–5.5V), 400 kHz in Fast mode (1.7–5.5V), and 1 MHz in Fast Mode Plus (2.5–5.5V). Operation above 400 kHz requires VCC ≥2.5V and proper bus capacitance control (≤100 pF) with appropriate pull-up resistors (≤1.3 kΩ for 1 MHz).

Does the AT24C04C-XHM-T require external pull-up resistors on SDA and SCL lines?

Yes, the AT24C04C-XHM-T requires external pull-up resistors on both SDA and SCL lines because SDA is open-drain and SCL is input-only. Recommended values are ≤10 kΩ for 100 kHz, ≤4 kΩ for 400 kHz, and ≤1.3 kΩ for 1 MHz operation - selected based on bus capacitance and rise-time requirements per I²C specification.

How does the write-protect (WP) pin function on the AT24C04C-XHM-T?

When WP is tied to VCC, the AT24C04C-XHM-T disables all write operations to its entire memory array. When WP is grounded, normal byte/page writes are enabled. If left floating, WP is internally pulled down to GND, enabling writes - but Microchip recommends hardwiring WP to avoid noise-induced glitches during operation.

What is the memory organization of the AT24C04C-XHM-T?

The AT24C04C-XHM-T is organized as 512 words × 8 bits (4,096 total bits), arranged in 32 pages of 16 bytes each. This structure enables efficient page-write operations (1–16 bytes per command) and supports both random and sequential read modes without address wraparound limitations.

Is the AT24C04C-XHM-T compatible with the AT24C04D-XHM-T in terms of pinout and software interface?

Yes, the AT24C04C-XHM-T is pin-to-pin and functionally compatible with the AT24C04D-XHM-T - sharing identical UDFN-8 package, pin assignment, I²C protocol, memory map, and command set. The AT24C04D-XHM-T adds enhanced ESD protection and slightly improved write timing but requires no hardware or firmware changes for drop-in replacement.