Microchip Technology AT24C04D-MAHM-E
- Part No.:
- AT24C04D-MAHM-E
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-UFDFN Exposed Pad
- Datasheet:
-
AT24C04D-MAHM-E.pdf
- Description:
- IC EEPROM 4KBIT I2C 1MHZ 8UDFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
AT24C04D-MAHM-E from Microchip Technology (formerly Atmel) is a 4-Kbit I²C-compatible serial EEPROM organized as 512 × 8 bits, operating from 1.7V to 3.6V, supporting Standard (100 kHz), Fast (400 kHz), and Fast Mode Plus (1 MHz at 2.5–3.6 V) interfaces, with hardware write protection via the WP pin, and used for nonvolatile parameter storage in embedded control systems.
For engineers reviewing the AT24C04D-MAHM-E datasheet, AT24C04D-MAHM-E pinout, AT24C04D-MAHM-E application, or AT24C04D-MAHM-E equivalent, key selection considerations include voltage range compatibility (1.7–3.6 V), I²C bus speed mode support, page write capability (16-byte pages), ultra-low standby current (≤0.8 μA), and hardware write protection behavior tied to the WP pin state.
Technical Context
The AT24C04D-MAHM-E functions as an I²C slave device with a fixed 7-bit device type identifier (1010b) and two hardware address bits (A1, A2), enabling up to four devices on one bus. It uses open-drain SDA/SCL with Schmitt-trigger inputs and internal noise filtering.
It implements a 32-page × 16-byte memory architecture with automatic address incrementing during sequential reads/writes, self-timed internal write cycles (≤5 ms), and acknowledge polling support to avoid fixed timeout delays. The WP pin controls full-array hardware write protection, sampled at Stop condition assertion.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 4 Kbit (512 × 8 bits), organized in 32 pages of 16 bytes - enables efficient byte- or page-level updates without erasing entire array. |
| Supply Voltage Range | 1.7 V to 3.6 V - supports direct interface with low-voltage microcontrollers (e.g., 1.8 V or 3.3 V logic domains). |
| I²C Speed Modes | 100 kHz (Std), 400 kHz (Fast), 1 MHz (FM+, 2.5–3.6 V only) - allows flexible timing budget allocation across system clock domains. |
| Write Cycle Time | ≤5 ms max self-timed write - eliminates need for external delay timers; ACK polling enables deterministic completion detection. |
| Endurance & Retention | 1,000,000 write cycles / 100 years data retention - suitable for long-life industrial logging and calibration storage. |
| Standby Current | ≤0.8 μA at 3.6 V - critical for battery-backed or energy-harvesting applications requiring multi-year quiescent operation. |
| Write Protection | Hardware-enabled via WP pin: high = full-array lock, low = normal write - prevents accidental overwrites during power transitions or firmware faults. |
Pinout & Package
AT24C04D-MAHM-E is supplied in an 8-lead SOIC package (JEDEC MS-012, 150 mil width). Pin 1 is NC (no connect); pins 2–3 are A1/A2 address inputs; pin 4 is GND; pin 5 is SDA (open-drain bidirectional data); pin 6 is SCL (input clock); pin 7 is WP (active-high write protect); pin 8 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| NC (Pin 1) | No-connect terminal | Not bonded internally; may be left floating or tied to GND - no electrical effect on operation. |
| A1, A2 (Pins 2, 3) | Hardware device address inputs | Select one of four possible I²C slave addresses (1010xxxA); pulled down internally if unconnected - ensures deterministic default addressing. |
| GND (Pin 4) | Power ground reference | Must be connected to system ground plane; serves as return path for all internal current paths and noise filtering circuits. |
| SDA (Pin 5) | Bidirectional serial data line | Open-drain output requiring external pull-up (≤10 kΩ); transmits/receives I²C data and ACK/NACK bits - shared across multiple slaves on same bus. |
| SCL (Pin 6) | Serial clock input | Master-generated clock controlling data sampling (rising edge) and output (falling edge); includes integrated Schmitt trigger and noise filter. |
| WP (Pin 7) | Write protect enable input | Active-high signal: high = inhibit all writes, low = allow writes - sampled at Stop condition, immune to mid-cycle toggling. |
| VCC (Pin 8) | Power supply input | Supplies core logic and EEPROM programming circuitry; must remain stable within 1.7–3.6 V during all operations including write cycles. |
Key Features
| Feature | Design Value |
|---|---|
| 16-byte page write mode | Enables burst programming of up to 16 contiguous bytes per write cycle - reduces bus overhead and total write time vs. byte-by-byte writes. |
| Schmitt-trigger & filtered inputs | Rejects fast transients and EMI on SDA/SCL lines - improves robustness in noisy industrial environments without external RC filtering. |
| Ultra-low standby current (0.8 μA max) | Minimizes battery drain in always-on or intermittently powered systems - extends operational life in metering, sensor nodes, and backup storage. |
| Internal address counter roll-over | Automatically wraps from last memory address to first during sequential read - simplifies firmware implementation of circular buffers or continuous streaming. |
| ACK polling support | Allows host to detect write completion in real time - eliminates fixed 5 ms delays and enables tighter scheduling in time-critical firmware. |
Applications
| Industrial Sensor Calibration Storage | Consumer Device Configuration Memory |
|---|---|
Use Scenario: Storing factory-calibrated offset/gain coefficients and temperature compensation tables for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed infrequently during startup or maintenance mode; operates at 100 kHz I²C speed with 1.8 V supply. Use Value: Ensures measurement accuracy remains traceable across product lifetime; hardware WP prevents corruption during brown-out events. |
Use Scenario: Holding user preferences (brightness, language, network SSID) and device-specific identifiers (MAC extension, serial number) in smart home hubs. IC Role / Device Role / Timing Role: Low-power configuration manager interfacing with 3.3 V MCU via 400 kHz I²C; retains data through >10⁶ power cycles. Use Value: Enables seamless user experience across reboots; 0.8 μA standby current extends battery backup duration beyond 5 years. |
| Medical Diagnostic Instrument Settings | Automotive Body Control Module NVM |
Use Scenario: Archiving diagnostic thresholds, alarm limits, and calibration history logs in portable ultrasound units with strict EMC requirements. IC Role / Device Role / Timing Role: Noise-immune EEPROM using Schmitt-triggered SDA/SCL; accessed during boot sequence at 1.7 V minimum supply. Use Value: Meets IEC 60601 immunity standards without added filtering; 100-year data retention satisfies regulatory record-keeping mandates. |
Use Scenario: Storing door lock actuator positions, mirror presets, and lighting profiles in automotive BCMs exposed to -40°C to +85°C ambient. IC Role / Device Role / Timing Role: Industrial-grade serial NVM with guaranteed operation across full temperature range; WP pin tied to MCU GPIO for dynamic protection. Use Value: Eliminates need for external voltage supervisors; 1M endurance supports daily reprogramming throughout vehicle service life. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STMicroelectronics M24C04-RMN6TP | Same 4-Kbit size, 1.7–5.5 V supply, but supports only up to 400 kHz I²C; no FM+ mode; WP pin active-low. | Requires level-shifting for 1.8 V systems; lacks 1 MHz option for high-throughput logging; active-low WP demands inverted control logic. | Preferred where wider voltage margin (up to 5.5 V) is needed and FM+ is unnecessary; verify WP polarity in firmware. |
| ON Semiconductor CAT24C04WI-GT3 | Identical 4-Kbit organization and 1.7–5.5 V range; supports 1 MHz FM+; WP pin active-high like AT24C04D-MAHM-E; RoHS-compliant 8-lead SOIC. | Drop-in replacement in most cases; same pinout and WP behavior; slightly higher max ICC2 (1.2 mA vs. 1.0 mA) during write. | Valid alternative when sourcing flexibility is required; validate timing margins under worst-case VCC/temperature conditions. |
Compared with M24C04-RMN6TP and CAT24C04WI-GT3, the AT24C04D-MAHM-E offers guaranteed 1 MHz operation within its native 2.5–3.6 V window and lower max write current, making it optimal for power-constrained, high-speed I²C subsystems where timing predictability and efficiency are critical.
Availability
AT24C04D-MAHM-E is available at Aetrix Electronics and suitable for industrial sensor calibration, consumer device configuration, medical diagnostics, and automotive body control modules requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for AT24C04D-MAHM-E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology acquired Atmel in 2016 and maintains full technical and manufacturing continuity for the AT24C04D family. Microchip is a global leader in microcontrollers, analog, and memory solutions, serving industrial, automotive, and communications markets.
The AT24C04D series was designed specifically for low-voltage, low-power I²C-based nonvolatile storage in space-constrained embedded systems - emphasizing reliability, noise immunity, and seamless integration with 8-/16-/32-bit MCUs.
FAQ
What is the maximum I²C clock frequency supported by the AT24C04D-MAHM-E?
The AT24C04D-MAHM-E supports 100 kHz (Standard Mode), 400 kHz (Fast Mode), and 1 MHz (Fast Mode Plus) - but FM+ operation requires VCC ≥ 2.5 V. At 1.7–2.4 V, only Standard and Fast Modes are guaranteed. This ensures interoperability across diverse MCU platforms while enabling higher throughput where supply voltage permits.
How does the WP pin function on the AT24C04D-MAHM-E?
The WP pin on the AT24C04D-MAHM-E is active-high: when pulled to VCC, it disables all write operations to the entire memory array; when pulled to GND or left floating (due to internal weak pull-down), writes are enabled. Its state is sampled at the Stop condition of each write command - changes during a write cycle have no effect.
Can the AT24C04D-MAHM-E be used with a 1.8 V microcontroller?
Yes - the AT24C04D-MAHM-E is fully specified for 1.7–3.6 V operation, including reliable I²C communication at 1.8 V. Its Schmitt-trigger inputs and noise-filtered SDA/SCL ensure robust signaling at low voltage, and its 0.08 μA typical standby current at 1.8 V makes it ideal for battery-sensitive designs.
What is the memory page structure of the AT24C04D-MAHM-E?
The AT24C04D-MAHM-E organizes its 512 bytes into 32 pages of 16 bytes each. Page writes are limited to addresses within the same page (bits A8–A4 identical); crossing a page boundary causes wraparound within that page. This structure enables efficient bulk writes while preventing unintended overwrites across page boundaries.
Does the AT24C04D-MAHM-E require external pull-up resistors on SDA and SCL?
Yes - the AT24C04D-MAHM-E has open-drain SDA and input-only SCL pins, both requiring external pull-up resistors. The datasheet specifies ≤10 kΩ for SDA; SCL pull-up value depends on bus capacitance and target speed - typical values range from 2.2 kΩ to 10 kΩ. Proper termination ensures valid I²C voltage levels and timing compliance.
AT24C04D-MAHM-E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-UFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8
- Memory Interface:
- I2C
- Clock Frequency:
- 1 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- 4.5 µs
- Voltage - Supply:
- 1.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TC)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-UDFN (2x3)
AT24C04D-MAHM-E FAQ
1.How can I place an order for AT24C04D-MAHM-E through Aetrix?
Please submit a Request for Quotation (RFQ) for AT24C04D-MAHM-E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for AT24C04D-MAHM-E reliable?
The price and inventory of AT24C04D-MAHM-E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for AT24C04D-MAHM-E is usually 5 days.
3.What payment methods are accepted for AT24C04D-MAHM-E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for AT24C04D-MAHM-E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for AT24C04D-MAHM-E?
AT24C04D-MAHM-E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your AT24C04D-MAHM-E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for AT24C04D-MAHM-E?
For technical support, including AT24C04D-MAHM-E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your AT24C04D-MAHM-E requirements.
6.How does Aetrix verify that AT24C04D-MAHM-E is sourced from the original manufacturer or authorized distributors?
All AT24C04D-MAHM-E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that AT24C04D-MAHM-E meets industry standards.
7.What is the process for return or replacement of AT24C04D-MAHM-E?
All AT24C04D-MAHM-E units undergo pre-shipment inspection (PSI). If there is an issue with AT24C04D-MAHM-E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The AT24C04D-MAHM-E part is unused and in its original packaging.
Return procedure for AT24C04D-MAHM-E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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